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Dynamic instantiation/removal of TB components?
Posts: n/a
Hello Gurus of VHDL,

I have synthesizable VHDL code for a receiver (my DUT).

In my VHDL testbench, I want to model an *arbitrary* number of
overlapping transmitters in the area, each of which can generate a
"long" waveform (2000 to 20000 clocked samples, depending on message

Can I dynamically (and at random) instantiate (and destroy) instances
of a transmitter model/component?

I'd like to have transmitters randomly enter and leave the reception
area, and while in range, independently of (and asynchronous to) each
other, transmit their signal to my DUT. The input to my DUT comes from
an A/D converter model, whose output should be the sum of all the
currently active transmitter signals.


Some considerations follow:

If not multiple dynamic instantiations of a transmitter "component",
might it be better to create ONE transmitter model that can generate an
arbitrary number of signals itself?

Since each transmitter's output is async wrt others, and the output
waveforms vary between 2000 and 20000 clock cycles, a single model (one
instance) would have to keep track of all state info (including time,
or relative time) for each waveform being generated.

If the number of overlapping transmitter waveforms is arbitrary, would
I have to use dynamic memory allocation (access types?) to do this?

Less elegant methods would include instantiating a fixed number of
simple transmitters, or writing an arrayed implementation of a
transmitter/summer. In either case, some upper limit on the number of
transmitters would likely be hardcoded.

Either way, I need to have ONE adder (with appropriate number of
inputs) summing the transmitter outputs and producing one output to
drive my A/D converter model.

I currently use an ugly, standalone C program to generate text files
that represent the summed (superimposed) overlapping waveforms. These
files are read in by the A/D converter model in my testbench, and
that's what drives the DUT.

C does not model the concurrency well, and the limitations of reading a
canned file (slow I/O, no dynamic adaptation of the transmitted
signals, difficulty in self-checking) are my motivations do this all
dynamically (in simulator memory).

I did something like the dynamic multiple instantiations in an Ada
project 15 years ago, but can't find the code or remember how I did it.

Would something like SystemC (which I barely know) constructors and
destructors make this easier, and integrate well into a VHDL (ModelSim)

Thanks very much for any and all constructive feedback. I really do
appreciate it.


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Posts: n/a
I do not understand fully what you want, but it sounds to me that the
following could help:

>Can I dynamically (and at random) instantiate (and destroy) instances
>of a transmitter model/component?


use a GENERIC noofwaves: natural;

In your testbench, use a generate statement to instantiate the

signal outs: std_logic_vector(noofwaves-1 downto 0;
for i in noofwaves-1 dowto 0 generate
WF: wavefrom PORT MAP (N=> i; O=> outs(i));
end generate;

GenSum: process(outs)
.. sum all outs
end process;

You can then generate waveform entities. Each of these could even read
from an input file

entity waveform is
port (N: in integer; O: out std_logic);
end entity;

architecture reader of waveform is
procedure waveform_from_file(no: integer; signal O: out std_logic) is
file wavefile : text := "waveform_" & integer'image(no);
... -- read values and times from wavefile (waveform_0,

You can define the generic and the architectures in a configuration.
This will enable you to use an "arbitrary" number of different
waveforms without defining a maximum at compile time.

Reply With Quote
Posts: n/a
you can also try having fixed number of multiple transmitters each
transmitting independently and so designed that each of them shut down
randomly for a random duration of time.

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