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problem with timing simulation

 
 
JEmoderatz@yahoo.com
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      08-09-2005
Hi

I have two problems when simulating a state machine after PAR (place
and route) using Modelsim6.0 and XST ISE6.3.

First problem is that I can not find the name of the state in the
signal list. So it is very hard to trace (debug). Are there any way to
see the name (or symbol) of the state?

Second problem is that I have following warning after PAR. It is not
working in timing simulation.

WARNING:NetListWriters:303 - Unable to preserve the ordering for port
bus mux_a on block using the data mux_a<0><1:0>.

Port ( clk : in std_logic;
rst : in std_logic;
...
mux_a : out array_mux);

In package, array_mux is defined

type array_mux is array (0 to 3) of std_logic_vector(1 downto 0);

Thankyou for the reply.

 
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ALuPin@web.de
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      08-09-2005
Second problem:

0 to 3 <--> 1 downto 0

See?

Rgds
André

 
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Duane Clark
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      08-09-2005
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:
> Second problem:
>
> 0 to 3 <--> 1 downto 0
>


In general that is perfectly acceptable, and I have done it several
times, though only on internal signals. I have not tried using a two
dimensional array on pin assignments.

If the PAR tool allows two dimensional arrays on pins, but did not allow
the dimensions to be in different directions, then I would consider that
to be a bug.

 
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JEmoderatz@yahoo.com
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      08-10-2005
Hi

Regarding 2nd problem, I did modification and the same problem occurred
-:

array_mux is array (3 downto 0) of std_logic_vector(1 downto 0);

I suspect that the port with 2 dimensional array type is not supported
by ISE PAR.

 
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ALuPin@web.de
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      08-10-2005
Where do you use that array_mux ?

In signal declaration within the VHDL architecture or as port type
declaration of the entity?

Rgds
André

 
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Ralf Hildebrandt
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      08-10-2005
(E-Mail Removed) wrote:


> Second problem is that I have following warning after PAR. It is not
> working in timing simulation.
>
> WARNING:NetListWriters:303 - Unable to preserve the ordering for port
> bus mux_a on block using the data mux_a<0><1:0>.
>
> Port ( clk : in std_logic;
> rst : in std_logic;
> ...
> mux_a : out array_mux);
>
> In package, array_mux is defined
>
> type array_mux is array (0 to 3) of std_logic_vector(1 downto 0);


Just to make shure: You did compile the package before the entity?


Is this the entity of your topmost component? Then it would be better to
break the 2D array down to a 1D vector.

Ralf
 
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