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Which is faster in ASIC: 2-input AND gate or a 2-input multiplexer

 
 
Weng Tianxiang
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      08-05-2005
Hi,
I would like to know from experienced ASIC designers the following
question:
Which is faster in ASIC circuit: 2-input AND gate or a 2-input
multiplexer in normal situation and why?

Thank you.

Weng

 
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TigerJade
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      08-05-2005
2-input muxer might be faster? An AND gate needs a NAND gate followed
by a inverter, I think.

 
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eNo
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      08-05-2005
"Weng Tianxiang" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
> Hi,
> I would like to know from experienced ASIC designers the following
> question:
> Which is faster in ASIC circuit: 2-input AND gate or a 2-input
> multiplexer in normal situation and why?


Generally, the and-gate would be faster. The mux has two levels of logic,
whereas the and-gate only has one. In FPGA land this isn't so clear: most
logic is implemented in "LUT" blocks, which are essentially muxes. As
always, YMMV.

--
`,,,,`,,,,`,,,,`,,,, `,,,,
,,`,,,,`,,,,`,,,,` ,,,,`,,
eNo
"Test everything; hold on to the good."


 
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Weng Tianxiang
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      08-05-2005
Hi,
Thank you for your inputs.

1. I misspell the question: it should be:
Which is faster in ASIC: 2-input NAND gate or 2-input multiplexer?

Actually in ASIC, one multiplexer comprises 2 pass gates, one is P-type
pass gate, another N-type pass gate. The select input is coupled to two
pass gate control input.

For a 2-input NAND, it comprises 4 pass gates and two inverters.

Thank you.

Weng


VC
|

 
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Ralf Hildebrandt
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      08-05-2005
Weng Tianxiang wrote:


> Which is faster in ASIC: 2-input NAND gate or 2-input multiplexer?


Just a note: If you write good VHDL code, the synthesis tool will do the
decision for you - depending on the library.


Ralf
 
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Kai Harrekilde-Petersen
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      08-05-2005
"Weng Tianxiang" <(E-Mail Removed)> writes:

> Hi,
> Thank you for your inputs.
>
> 1. I misspell the question: it should be:
> Which is faster in ASIC: 2-input NAND gate or 2-input multiplexer?
>
> Actually in ASIC, one multiplexer comprises 2 pass gates, one is P-type
> pass gate, another N-type pass gate. The select input is coupled to two
> pass gate control input.
>
> For a 2-input NAND, it comprises 4 pass gates and two inverters.


Rubbish. A 2-input NAND gate can be made out of 4 transistors, and is
about the fastest gate you can come up with in any CMOS technology
(well, either that or a 2-input NOR gate).


Kai
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Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
 
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Weng Tianxiang
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      08-05-2005
Hi Kai,
It is not rubbish.

I really don't know and really want to know. Could you please refer to
any books or materials that contain its schematics.

What I read is that it comprises 4 pass gates and two inverters.

Thank you.

Weng

 
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Weng Tianxiang
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      08-05-2005
Hi Kai,
You are right.

NAND comprises 2 P-type pass gates serial coupled to VC and 2 N-type
pass gate parallel coupled to ground and control input of each P-type
pass gate and N-type pass gate is coupled to one of input.

One 2-input multiplexer has a P-type pass gate and a N-type pass gate.
Their select input terminal are tied together and their 2 input
terminal are coupled to 2 inputs and their outputs are connected
together.

Which one is faster? Can you give some data on them. I don't have ASIC
experiences and don't have its related time estimate software
experiences. I want someone to provide some tips on its speed level.

Weng

 
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Kai Harrekilde-Petersen
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      08-06-2005
Hi Weng,

"Weng Tianxiang" <(E-Mail Removed)> writes:

> NAND comprises 2 P-type pass gates serial coupled to VC and 2 N-type
> pass gate parallel coupled to ground and control input of each P-type
> pass gate and N-type pass gate is coupled to one of input.
>
> One 2-input multiplexer has a P-type pass gate and a N-type pass gate.
> Their select input terminal are tied together and their 2 input
> terminal are coupled to 2 inputs and their outputs are connected
> together.
>
> Which one is faster? Can you give some data on them. I don't have ASIC
> experiences and don't have its related time estimate software
> experiences. I want someone to provide some tips on its speed level.


It's long since I did full custom layout and SPICE simulations on the
layout, so I can't give you have hard data. But a NAND2 gate in a
commercial 130nm process is less than 100psec (depending on output
drive etc).

In the standard 2-input NAND implementation each input will see a
p-mos and an n-mos gate, and the output drive is directly from
VDD/VSS.

Time for some ascii-art (please use a fixed-pitch font when viewing this):

VDD
-------------
| |
|- |-
A-o| B-o|
|- |-
| |
+------+--- Y
|
|-
A--|
|-
|
|-
B--|
|-
|
-------------
VSS

Pass-gate/mux implementation:

B
|
o
---
| |
VSS--- -----+
| | |
--- |
| |
+--!B +---Y
| |
o |
--- |
| | |
A--- -----+
| |
---
|
|
B

(please bear with my lazyness - !B is input B inverted)

The first implementation requires 4 transistors, is quite symmetric
wrt rise/fall time and delay from input to output.

The second will have a inferior drive to VDD/VSS when B=1 and good
drive to VSS when B=0. Input delay timing will obviously be different
for the two inputs, and it's going to take up more area (6
transistors).

I'd seriously doubt that the second implementation can be better than
the first implementation on any parameter (area, timing, power) -
assuming they are designed for driving the same output load, and
having /reasonably/ identical delay timing from A and B to Y.

Using pass-gates to implement complex logic can be very efficient,
when you are designing a well-controlled full-custom block (e.g.
ALU/MUL/RAM/CAM blocks, where the signal will be 'refreshed' before it
is sent outside the block), but for fundamental gates like a NAND2
gate I would say that it's not their day anymore.

For 180nm and below, most of the delay is not in the gates themselves,
but normally in the wires between the gates. Hence, you need a good
clean drive out of your gate onto the next, in order to get the best
timing.

I hope this has answered your questions.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>
 
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Weng Tianxiang
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      08-07-2005
Hi Kai,
Thank you very much. I am doing some important patent applications that
can be drawn as either one. I don't have any experiences with ASIC,
even though I have lot of FPGA experiences.

I see the following multiplexer implementation in some approved
patents.
S
|
o
---
| |
I1--- -----+
+ --- O
I2--- -----+
| |
---
|
S

What I really want to compare is which is faster: 2-input AND gate and
a mulitplexer on speed.

Based on your advice, I will change my drawing in the application.

Later I will send my patent application to you after it is mailed to
USPTO.

If you have more information to provide, please let me know.

Weng

 
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