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Legality of type conversion on instance ports?

 
 
Brandon
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      08-03-2005
I'm experiencing an error using XST during synthesis involving a type
conversion on a port instance:
http://www.xilinx.com/xlnx/xil_ans_d...eID=1&iCountry...


Is this legal syntax in the vhdl standard?

I was told by a Xilinx applications engineer that they don't have a fix
and I have to do the workaround. What a pain... Do the other synthesis
tools support this syntax?

 
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Jim Lewis
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      08-04-2005
Brandon
If you want help, post your code. While the general
case should work, there are many specific errors
that you could be tripping on.

Also you did not post the entire link, so it is difficult
to see which answer page you are referring to.

Cheers,
Jim
> I'm experiencing an error using XST during synthesis involving a type
> conversion on a port instance:
> http://www.xilinx.com/xlnx/xil_ans_d...eID=1&iCountry...
>
>
> Is this legal syntax in the vhdl standard?
>
> I was told by a Xilinx applications engineer that they don't have a fix
> and I have to do the workaround. What a pain... Do the other synthesis
> tools support this syntax?
>



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Jim Lewis
Director of Training (E-Mail Removed)
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
 
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