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Conditional compilation in VHDL

 
 
avishay
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      08-01-2005
Hello all,
I'm designing a testbench that should work on a real device (i.e.
synthesizable). When working that way, it receives clock and reset from
and external source. However, when I simulate it (I use Modelsim) I
have to generate clock and reset myself, using unsynthesizable code. My
question is whether there is a way to make a single source file compile
differently in the synthesizer (I use Quartus) and in the simulator.
Thanks for any help

Avishay Orpaz

 
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ALuPin@web.de
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      08-01-2005

avishay schrieb:

> Hello all,
> I'm designing a testbench that should work on a real device (i.e.
> synthesizable). When working that way, it receives clock and reset from
> and external source. However, when I simulate it (I use Modelsim) I
> have to generate clock and reset myself, using unsynthesizable code. My
> question is whether there is a way to make a single source file compile
> differently in the synthesizer (I use Quartus) and in the simulator.
> Thanks for any help
>
> Avishay Orpaz


Why not use a different testbench u2 (not synthesizable) to test
your design i1 + synthesizable "testbench" u1 ?

i1 and u1 could have one top level file t1 in which i1 and u1 are
instantiated and conncected.

t1 could then be instantiated in u2.

Rgds
André

 
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Neo
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      08-01-2005
just create a clock and reset generation module and connect it to your
top level for simulation.

 
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Mike Treseler
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      08-01-2005
avishay wrote:

> question is whether there is a way to make a single source file compile
> differently in the synthesizer (I use Quartus) and in the simulator.


Not without using a separate preprocessor step.
Standard practice is to put the sim testbench
in a separate file, say test_mydesign.vhd.
The testbench instances my_design
in the file my_design.vhd


-- Mike Treseler
 
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Andy Peters
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      08-01-2005
avishay wrote:
> Hello all,
> I'm designing a testbench that should work on a real device (i.e.
> synthesizable). When working that way, it receives clock and reset from
> and external source. However, when I simulate it (I use Modelsim) I
> have to generate clock and reset myself, using unsynthesizable code. My
> question is whether there is a way to make a single source file compile
> differently in the synthesizer (I use Quartus) and in the simulator.
> Thanks for any help


Create a top-level testbench generic called SYNTHSIM that's 1 if you're
creating the synthesizable version and 0 if doing functional (ModelSim
testbench) simulation. Put the clock and reset instances/logic in a
generate block that generates that logic if SYNTHSIM = 0.

=-a

 
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