Velocity Reviews > VHDL > Decreasing memory size

# Decreasing memory size

sunny
Guest
Posts: n/a

 08-01-2005
Hi all,

I want to compare a part of a sequence of data ie if data is 20-bits I
want to compare only the 1st MSB. The detailed problem is as follows:

The 20-bit data is stored in 4 RAMs each of size R*20-bits where R is
the size of the RAM. My output is a 20-bit element array of length R. I
would like to compare the MSBs of the data stored in ith address of
each RAM. After every cycle the data of ith address of a RAM is shifted
to the same address of next memory. So RAMs are acting in the
shift-register fashion:
====== ====== ====== ======
--> |RAM1| --> |RAM2| --> |RAM3| --> |RAM4| --->
====== ====== ====== ======

So for every input at RAM1, I have outputs of all the 4 RAMs taken from
the same address (All 4 RAMs are operated by the same address counter).

If in x-out-of-5 (where x is prespecified and can range from 1 to 5)
cases, MSB = '1', the ith element of my output will be as follows:
output(i) <= '1' & ith_element_of_RAM2 (19 downto 0). If in x-out-of-5
cases, MSB != '1', then output(i) <= (others => '0').

============================
Working on the problem I realized I need not to keep all 5 memories of
size R*20-bits. Since the 19downto0 bits of the output always take up
data from the 2nd RAMs, I need to store only MSB of the incoming data
in 3rd and 4th RAMs. This means last two RAMs can have size R*1-bit and
they need to take only MSB of the data coming from RAM2.

=============================

In a similar fashion, is it possible to reduce size of even RAM1?
Although output never takes up data from RAM1, the same data goes to
RAM2 in the next cycle and hence cannot be truncated. Is there any way
to still reduce memory utilization here. Because in my case R=4000 and
is taxing a lot on my FPGA.