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Question about shifting

 
 
jahaya@gmail.com
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      07-22-2005
Hello Folks,

I would like to shift some set of bits in a std_logic_vector array

CALCROCESS(CLK)
signal REG_S: std_logic_vector (15 downto 0);

begin

if (CLK = '1' and CLK'event) then
REG_S(15 to 13) <= REG_S(14 to 12);
REG_S(11 to 6) <= REG_S(10 to 5);
REG_S(4 to 1) <= REG_S(3 to 0);
end if;
end process CALC;

I am getting an warning message as "The range is "null range" and error
message as "Direction of the discrete range must be the same as that of
the prefix of the slice name"

I didnt understand the error ? Can anyone explain this prob ?

Thanks in advance,
ALI

 
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jahaya@gmail.com
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      07-22-2005
I guess I should use as below :

REG_S(15 downto 13) <= REG_S(14 downto 12);
REG_S(11 downto 6) <= REG_S(10 downto 5);
REG_S(4 downto 1) <= REG_S(3 downto 0);

ALI

 
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