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Hi,

I have some doubts concerning the following problems:

In my design I have an 8bit bidiretional bus "Data_ulpi".
When the external module drives data into my FPGA
I have to read that data and respond immediately that is
I have NO time to synchronize the data with 2-stage-FFs/FIFO.

.... NO time because the external module is expecting response on the
next clock cycle.

I have read several posts in this newsgroup
explaining that the state machine would have to be very tricky
to handle unregistered inputs.

So how do I have to place bidirectional bus and control signals
to have at least a chance of doing a good job ?
What constraints do I have to take into consideration in that
special case for tSU/tH ?

Thank you for your advice.

Rgds
André

Some additional info:

The clock of the FSM is provided by the external module.

Rgds
André

We are in a causal world, so there is always an event which signals
valid data, so NO time seems to be an exaggeration.

Without more information, the following can be said:

> You can think of using latches. The read event will latch the last data.

> You can delay signals and data appropriately to generate proper setup/hold conditions. Using delays, you can even design circuitry handling negative setup times properly etc.


> The latched data can then be treated using 2-stage ffs or any other possibilties to handle unsychronized data.

Hubble.

I have never used latches. What is the problem about them ? Do Fitter
treat them predictable ?

André

I have read the following in one post discussing latches:
"None of the above applies to FPGA, you will have no control over
anything and your timing will be horrible so forget it. "


Comments ?

wrote:

> ... NO time because the external module is expecting response on the
> next clock cycle.

That's one external clock cycle, not zero.
Use a fpga clock at least twice that fast.
Send a handshake while you synchronize the data strobe.

> I have read several posts in this newsgroup
> explaining that the state machine would have to be very tricky
> to handle unregistered inputs.

Any synchronous design will have problems with asynchronous
inputs. Note that registered inputs may or may not
be synchronous to the fpga clock.


-- Mike Treseler

wrote:
> Some additional info:
>
> The clock of the FSM is provided by the external module.
>
In that case, you can just turn around the data strobe
as a handshake and latch the data on the same
clock tick.

-- Mike Treseler

I think we need a better statement of the problem.
You have an 8-bit wide incoming data bus. Is there a clock that defines
valid data? What is the timing of that clock or clock edge? If there
is no clock, how do you know that there is new data? What if the new
data is identical with the old data?

Peter Alfke

wrote:
> I have read the following in one post discussing latches:
> "None of the above applies to FPGA, you will have no control over
> anything and your timing will be horrible so forget it. "

In a synchronous design, even one with 30,000
flops, I need only one synthesis constraint, Fmax.
Synthesis is a formality.

In an asynchronous design I need to constrain
setup and hold times to every flop.
Synthesis is tedious at best.

-- Mike Treseler

Andre,

There are a few alternatives.
I am doing something similar in my design right now, but it depends on the
speed of your clock/data rate and whether it's smooth or gapped.

(*) You can generate a higher clock and do everything with it - nice, clean
and quiet. In this case, use OFFSET constraint for external clock. You can
apply either internal or EXTERNAL setup/hold settings for the OFFSET
constraint (external means the specs of the external device, but make them a
little harder than the spec).
(**) You can try some very nice asynchronous switching by latches,
but......................................... I am not a big fan of it.
(***) NO time at all, try PAD to PAD delay, which you can contraint for the
cases you have a PAD ==> combinational_logic ==> PAD.

If you could give a few more details...

Hope this helps.
Vladislav

P.S. .

<> wrote in message
news: oups.com...
Hi,

I have some doubts concerning the following problems:

In my design I have an 8bit bidiretional bus "Data_ulpi".
When the external module drives data into my FPGA
I have to read that data and respond immediately that is
I have NO time to synchronize the data with 2-stage-FFs/FIFO.

.... NO time because the external module is expecting response on the
next clock cycle.

I have read several posts in this newsgroup
explaining that the state machine would have to be very tricky
to handle unregistered inputs.

So how do I have to place bidirectional bus and control signals
to have at least a chance of doing a good job ?
What constraints do I have to take into consideration in that
special case for tSU/tH ?

Thank you for your advice.

Rgds
André