On Mon, 04 Jul 2005 17:42:13 -0400, "charsi"
<> wrote:
>i wrote a code for a RAM, which essentially comprises of an array. Now i
>want to read some location in the RAM (array) in some other file..here
>lies the problem..
>
>1. simply accessing that array gives me error.
>2. i tried writing the array declaration in package, i dont get any syntax
>error but then i dont get any data either.
Oh dear.
Please repeat after me, very slowly and very many times:
VHDL IS NOT C.
If you are writing software in VHDL (for example, if you are
creating a big complicated test bench) then it is sometimes
reasonable to use shared variables declared in packages.
However, the behaviour of shared variables changed
significantly in VHDL-2002 and it's not a good place for
beginners to start their VHDL learning curve.
If you are writing hardware, then you must understand how
VHDL tries to represent hardware. Of course it gives an
error to access the array from somewhere else. I don't know
whether you have ever used a real RAM device, but even if you
haven't I guess you would not expect to read its contents
by removing its package and looking inside. Why, then, do
you expect VHDL to behave like that? To access a RAM you
must manipulate its connections (ports) correctly - supply
an address, wiggle its read strobe and chip select signals,
and pick up the data.
Tell us more and we may be able to guide you better. But
please don't forget to learn the very basic stuff about
entities, ports and signals. The comp.lang.vhdl FAQ will
point you to some excellent textbooks and online advice.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
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