memory creation with record

hello
in my design iam trying to create my memory with record type. its shows
error(type error resolving index expression ) while doing simulation with
model sim.
why iam using like this is,i read somewhere that synopsys gives good
result if you use record type instead of double dimensional array.
please guide me what ia the problem with below code.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use work.contr_pak.all;

ENTITY mux_mem IS
generic(addr_width: integer:=8;
data_width: integer :=24);

port(
clk : in std_logic;
reset : in std_logic;
w_addr : in std_logic_vector(addr_width-1 downto 0); --write
address (state bits)
r_addr : in std_logic_vector(addr_width-1 downto 0); -- read
address (state bits)
data_in : in std_logic_vector(data_width-1 downto 0); -- input
dara
data_out : out std_logic_vector(data_width-1 downto 0);
--output data ( input ctrl width

-- incl..no )
we : in std_logic;
re : in std_logic);
END ENTITY mux_mem;

--
ARCHITECTURE mux_mem_beh OF mux_mem Is

type mux_mw is record --mem width
temp : std_logic_vector( data_width-1 downto 0);
end record;
type mux_mem is array (addr_width-1 downto 0)of mux_mw; --mem size
--type mux_mem is array (addr_width-1 downto 0) of
std_logic_vector(data_width-1 downto 0);
signal ram1: mux_mem;

begin

process(clk,reset)
begin
if reset = '0' then
--w_addr <=(others=>'0');
--r_addr <=(others=>'0');
data_out <=(others=>'0');

elsif clk'event and clk='1' then
if re = '1' then
data_out <= ram1(conv_integer(r_addr));
-- data_out<= ram1(vect_to_int(r_addr));
else
data_out <= (others=>'0');
end if;

if we = '1' then
ram1(vect_to_int(w_addr)) <= data_in;
end if;
end if;

end process;

END ARCHITECTURE mux_mem_beh;

srinukasam

On Thu, 30 Jun 2005 12:58:13 -0400, "srinukasam"
<> wrote:

>in my design iam trying to create my memory with record type. its shows
>error(type error resolving index expression ) while doing simulation
[...]
>please guide me what ia the problem with below code.

Problem (1), not so important:
you're using both STD_LOGIC_UNSIGNED and STD_LOGIC_ARITH.
Learn about NUMERIC_STD.

Problem (2), giving your error:

> type mux_mw is record
> temp : std_logic_vector( data_width-1 downto 0);
> end record;
> type mux_mem is array (addr_width-1 downto 0)of mux_mw;
> signal ram1: mux_mem;
[...]
[reading]
> data_out <= ram1(conv_integer(r_addr));
[writing]
> ram1(vect_to_int(w_addr)) <= data_in;

ram1(N) is an expression of type mux_mw, but you are trying
to copy it to/from a std_logic_vector. Instead, you need
something like
ram1(N).temp
to access the std_logic_vector component of the record.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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