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Integer to std_logic_vector?

 
 
Sebastian Eggers
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      06-29-2005
Hi,

i have to count several values from 0 to 99, at the moment i do it in an
array of integer 0 to 99.

As output-port i use a std_logic_vector(6 downto 0), but i may change
this if necessary.

How can i convert the integer to the vector? i have no idea and not
found any solutions yet. Any hint would be helpful

thanks
Sebastian
 
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Neo
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      06-30-2005
use the conversion functions in the ieee numeric package or the
std_logic package

 
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ALuPin@web.de
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      06-30-2005
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

conv_std_logic_vector(7, 9);

converts integer 7 to a std_logic_vector with 9 bits.

Rgds
André

 
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Nicolas Matringe
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      06-30-2005
> use ieee.std_logic_1164.all;
> use ieee.std_logic_arith.all;
>
> conv_std_logic_vector(7, 9);
>
> converts integer 7 to a std_logic_vector with 9 bits.


Nope! Please stop using std_logic_arith package.

use ieee.numeric_std.all

std_logic_vector(to_unsigned(natural_number, nb_bits));

Nico

 
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Galloth Galloth is offline
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Posts: 1
 
      11-09-2006
Why we should stop using std_logic_arith package?
 
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Vivek Dhiman Vivek Dhiman is offline
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Posts: 1
 
      07-26-2010
It's simple firstly you should include these libraries
------------------------------------------
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
-------------------------------------

now suppose you have declared
signal x : integer;
signal sig : std_logic_vector (7 downto 0); --- (I am taking here length as 8 you take as much as you want)

-------------------------------------------------
x <= 2;
sig <= std_logic_vector (to_unsgined(x,8 )) -- x is the integer and 8 is the length of std_logic vector sig . If your siganl's length is n (suppose) then you have to write...


sig <= std_logic_vector (to_unsgined(x,n)) -- replace n by length of the vector decalred by you.
 
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joeblow joeblow is offline
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Join Date: Jul 2010
Posts: 1
 
      07-26-2010
-- Generally preferably to only use "official" IEEE libraries
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

-- ...

-- "natural" means >= 0. Add range to x to help synthesis
constant NUM_BITS : natural := 8;
signal x : natural range 0 to 2**NUM_BITS-1;
signal vect : std_logic_vector(NUM_BITS-1 downto 0);

-- ...

-- By using LENGTH attribute, any change to vect is handled automatically
-- Could also just use NUM_BITS
x <= 2;
vect <= std_logic_vector(to_unsigned(x, vect'LENGTH));


The above code might look a little more complex, but by using constants and attributes, your code will be much more forgiving of changes in the future.
 
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debayan_p debayan_p is offline
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Join Date: Jun 2009
Posts: 23
 
      08-03-2010
I guess using IEEE official libraries is better coz they will not cause synthesis problems at a latter stage.

There are many synthesis tools, all of them don't follow the same libraries!!

Cheers,
Debayan
 
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Fleetfoot Fleetfoot is offline
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Join Date: Nov 2011
Posts: 2
 
      11-11-2011
Is there a way to do this when the integer is a generic? The LENGTH attribute doesn't apply and I need something equivalent to declare vect (in the above example) as:

signal vect : std_logic_vector(x'HIGH-1 downto 0);

This is legacy code that is being upgraded and the module is used in various places with different generic values from 13 to 25000 so using a single common width is not feasible.

Thanks
George
 

Last edited by Fleetfoot; 11-11-2011 at 10:58 AM..
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joris joris is offline
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Posts: 152
 
      11-12-2011
Given that you are talking about generics, you could just calculate the length 'compile-time' using a log2() function (I think you'll have to write the function yourself, but that is trivial)
 
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