netlist from VHDL code

Hi,

I am trying to simulate a cache compressor with some 8k data lines. I
mean 8k lines are the input from L1 cache to the compressor. The
compressor send the compressed output to the L2 cache or main memory.
In this simulation I don't even want to verify the functionality - as
an function(algorithm choosen for this compressor) can be implemented
in a circuit form. I would like to find out the critical path of the
circuit.

Now my problem is since the circuit is too big(too many data lines),
I don't want to draw the schematic. So Can I write the VHDL code for
the circuit and get a netlist from the code. If I can do that, then I
can run the pathmill to find the critical path of the circuit and so as
the max. delay.

Pls let me know if you guys have any suggestions.

Thanks

Ruby