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#1 |
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Hi,
in my simulation I have a dual port Ram (from QuartusII v.5.0) which is initialized to all zeros with a hex file. My problem: After some write operations into the RAM (32 write positions are provided by a FIFO module) I want to reset my design in my VHDL simulation (Modelsim) because the FIFO is empty. The present state of design does not allow to put back the write positions into my FIFO. After the FIFO is empty I could reset my design within my testbench. But the contents of the RAM should also be resetted or rather be initialized again with zeros. I could step through my RAM and write at each address zeros into it but that takes too long for simulation. The hex file seems to have a bearing on initialization only at the beginning of the simulation. Is there some possibility to initialize the RAM during simulation by means of the hex file ? Any suggestions are appreciated. Rgds André ALuPin@web.de |
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#2 |
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Posts: n/a
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wrote:
> After the FIFO is empty I could reset my design within my testbench. Yes, just push more data in using the testbench. > But the contents of the RAM should also be resetted or rather > be initialized again with zeros. That's not what will happen on the bench. A fifo can only access data it has pushed in. You want 'U's elsewhere to make sure your head and tail counters are working ok. -- Mike Treseler Mike Treseler |
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#3 |
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Posts: n/a
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Hi Mike,
thank you for your answer. In a later stage of the design the read positions of the RAM will be pushed back into the FIFO whereas the corresponding entry in the RAM will be cleared that is filled with zeros. But right now I want to perform more functional test sequences with regard to writing positions in the RAM. But since there are only 32 "positions" available I'd need to reset the content of the RAM after 32 write actions into it. Rgds André Mike Treseler schrieb: > wrote: > > > > After the FIFO is empty I could reset my design within my testbench. > > Yes, just push more data in using the testbench. > > > But the contents of the RAM should also be resetted or rather > > be initialized again with zeros. > > That's not what will happen on the bench. > A fifo can only access data it has pushed in. > You want 'U's elsewhere to make sure your > head and tail counters are working ok. > > -- Mike Treseler ALuPin@web.de |
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#4 |
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Posts: n/a
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Any further suggestions ?
Rgds André ALuPin@web.de |
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