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#1 |
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hello
can i assign a std_logic vector to array of same bits. suppose.. signal vec:std_logic_vector(15 downto 0); type arr is array(o to 3) of std_logic_vector(0 to 3); .... arr <= vec; above mentioned code is right or wrong, if wrong is there any other way to assign std_logic_vector to array. thank you srinukasam |
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#2 |
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Posts: n/a
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There are 3 errors in your code. Since vec is a 16-bit vector you
cannot assign it to a 4-bit vector. When you assign a vector to an array of vectors you must specify an index. Also, you created the type arr, but did not declare a signal of that type. You can't make an assignment to a type. The following example may help. type arr is array(0 to 3) of std_logic_vector(15 downto 0); signal arr_a : arr; signal vec_0, vec_1, vec_2, vec_3 : std_logic vector(15 downto 0); .... arr_a(0) <= vec_0; arr_a(1) <= vec_1; .... I hope this helps. Charles charles.elias@wpafb.af.mil |
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#3 |
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hello
i ahve problem with generics and array in my code.its like this generic (width:=16 --t_width :integer:= 8; t_widths:=integer:=3; t_size:= integer:=3); signal ctrl:std_logic_vector(width-1 downto 0) type ctrl_gen array(o to t_size)of std_logic_vector(0 to t_widths) now i need a logic to assign ctrl(vector) to ctrl_gen(array). thank you srinukasam |
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#4 |
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Posts: n/a
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Homework?
Give directions not solutions. A. On Mon, 27 Jun 2005 05:54:43 -0400, srinukasam wrote: > hello > can i assign a std_logic vector to array of same bits. > suppose.. > > signal vec:std_logic_vector(15 downto 0); > type arr is array(o to 3) of std_logic_vector(0 to 3); > ... > arr <= vec; > > above mentioned code is right or wrong, if wrong is there any other way to > assign std_logic_vector to array. > > thank you Me |
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#5 |
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Posts: n/a
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hi friend
try this arr(0)<= vec(15 downto 12); arr(1)<= vec(11 downto arr(2)<= vec(7 downto 4); arr(0)<= vec(3 downto 0); it is immpossible to assign vec directly to arr. you have to specify the address of arr and also break down the vector to 4 bits because ur array is of 4 bits.ok try this viku |
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#6 |
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Posts: n/a
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Here is another more generic way using a generate loop. If you were doing this in several places I would create a function to do it. Note I changed the indexing of the array elements to use "DOWNTO" instead of "TO". CONSTANT VEC_WIDTH : integer := 16; CONSTANT ARR_SIZE : integer := 4; CONSTANT ARR_ELEM_WIDTH : integer := 4; SIGNAL vec : std_logic_vector(VEC_WIDTH-1 DOWNTO 0); TYPE arr IS ARRAY(0 TO ARR_SIZE-1) OF std_logic_vector(ARR_ELEM_WIDTH-1 DOWNTO 0); .... arr_assign_gen : FOR i IN 0 TO ARR_SIZE-1 GENERATE arr(i) <= vec(i*ARR_ELEM_WIDTH-1 DOWNTO (i-1)*ARR_ELEM_WIDTH); END GENERATE arr_assign_gen; combinational.logic $ soc-ip.com |
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