Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Question to resolved signals, transport delay

Reply
Thread Tools

Question to resolved signals, transport delay

 
 
lundril@gmx.de
Guest
Posts: n/a
 
      05-06-2006
Just a short question to the VHDL experts.
Assume we have the following TestBench

-------

library IEEE;
use IEEE.std_logic_1164.all;

entity TestBench is
end TestBench;

architecture behaviour of TestBench is

signal test : STD_LOGIC := '0';

begin
test <= transport '1' after 3 ns;
test <= transport '0' after 5 ns;
end behaviour;

------

Now which output wave-form is expected for "test" ?

I thought it should be:

0 at 0 ns (initial value because of declaration)
1 at 3 ns (first signal assignment becomes active).
X at 5 ns (two drivers '1' and '0', resolved to 'X').

But running it through a VHDL simulator gave

0 at 0 ns
X at 3 ns
X at 5 ns

Now I'm not at all sure why that happens and what the correct waveform
is for the "test" signal according to the VHDL2000 language reference.
Is this a bug in the VHDL simulator or what ?

Any comments ?

so long
lundril

 
Reply With Quote
 
 
 
 
Marcus Harnisch
Guest
Posts: n/a
 
      05-08-2006
Hi lundril,

http://www.velocityreviews.com/forums/(E-Mail Removed) writes:

> architecture behaviour of TestBench is
>
> signal test : STD_LOGIC := '0';
>
> begin
> test <= transport '1' after 3 ns;
> test <= transport '0' after 5 ns;
> end behaviour;
>
> [results in]
>
> 0 at 0 ns
> X at 3 ns
> X at 5 ns


Every signal driver performs the following steps upon execution:

- Delete all currently scheduled events

- Add own waveform

This means that since both drivers get executed at time 0, depending
on execution order, they will overwrite each other's scheduled event
list. It happens that both drivers "agree" on a value up until
t=3ns. So everything is fine up to that time. What happens after that
is not determined and results in an undefined value.

Hope that helps,
Marcus
 
Reply With Quote
 
 
 
 
KJ
Guest
Posts: n/a
 
      05-08-2006
The two assignments to signal 'test' get evaluated concurrently so it's
like having two outputs driving the same signal at the same time. As
long as the two outputs are the same things look good, when they differ
you have problems...which is when the simulator is saying that they are
'X' (because one of the equations is trying to drive it to '0', the
other to '1'.)

To get the behaviour that I suspect you were looking for you need to
embed those two lines in a process and probably add some wait
statements. Changes shown below

architecture behaviour of TestBench is
signal test : STD_LOGIC := '0';

begin
process
begin
test <= transport '1' after 3 ns;
wait for 3 ns;
test <= transport '0' after 5 ns;
wait for 5 ns;
end process;
end behaviour

Alternatively, maybe you had intended for 'test' to go to '1' at t=3ns,
and then 2 ns later (at t=5 ns) have it go back to '0'. If that's the
case, then you need to simply have the following

architecture behaviour of TestBench is
signal test : STD_LOGIC := '0';
begin
test <= transport '1' after 3 ns, '0' after 5 ns;
end behaviour

Not sure exactly what you're looking for it to do, but probably one of
these two will get you moving in the correct direction. The basic
problem with your code that is causing the 'X' is having two concurrent
statements assigning to the same signal.

KJ

 
Reply With Quote
 
lundril@gmx.de
Guest
Posts: n/a
 
      05-08-2006
Hello KJ,
Hello Marcus,

thanks for your input. Basically I don't try to do anything useful;
I just try to understand the real insides of the VHDL driver model.

So with the code I gave I expected the waveform
0 ns => wSig = 0
3 ns => wSig = 1
5 ns => wSig = X

As far as I understand the X should be the result from the resolution
function of
STD_LOGIC which basically says that if a signal is driven by two
sources with
'1' and '0', then the resulting signal is 'X'.

(As far as I understand the VHDL spec, the second signal assignment is
completely independent from the first signal assignemt. So it doesn't
"delete"
anything from the signal waveform.
A deletion only happens if you do something like this:
-------------
signal clk : STD_LOGIC := '0';
signal aaa: STD_LOGIC;
signal bbb: STD_LOGIC;
begin
clk <= not clk after 5 ns;
aaa <= clk after 8 ns; -- will stay "U", because we don't use
"transport".
bbb <= transport clk after 8 ns; -- will be like clk only 8 ns
delayed.
-------------
)

Now what I don't understand is why I get the 'X' already at 3 ns.
So what I get is
0 ns => wSig = 0
3 ns => wSig = X
5 ns => wSig = X

I don't understand why at 3 ns I get a "X". I read the VHDL spec in
more detail
now, an I gather that at 3 ns there is only one source active
(the first signal assignment) and so the simulator shouldn't output a
"X", but a "1".
(I tested this with ModelSim 6.0c, Altera Edition, with
ActiveHDL-6.2 and ActiveHDL-7.1, and all of these give "X" after 3
ns.)

What's even stranger: I modified the code to the following:

--------------------------
library IEEE;
use IEEE.std_logic_1164.all;

entity TestBench is
end TestBench;

architecture behaviour of TestBench is

signal test : STD_LOGIC := 'Z';

begin
test <= transport '1' after 3 ns;
test <= transport '0' after 5 ns;
end behaviour;
---------------------------------------------------

Now I get in ActiveHDL 6.2/ 7.1 and Modelsim 6.0c:

0 ns => test = Z
3 ns => test = 1
5 ns => test = X

So this is what I would expect: At "0 ns" only the initialization value
is driven; this
gives "Z". At 3 ns '1' is driven which results in '1', At 5 ns '0' and
'1' are driven
which results in 'X'.

So to me this seems like the simulator somehow interprets the
initialization
value as driver. So the X after 3 ns in the original code comes from
the
fact that the driver was initialized with "0" and then when the '1' is
driven
the "0" from the initialization collides with the '1' from the "after
3ns" assignment.

For me that still sounds like the simulator doesn't behave according to
the VHDL
specification...

so long
lundril

 
Reply With Quote
 
lundril@gmx.de
Guest
Posts: n/a
 
      05-08-2006
Arg, okay I found the paragraph which explains this:

The

signal test : STD_LOGIC := '0';

means that '0' is a defaulft value for any driver of test. This means
that

test <= transport '1' after 3 ns;
test <= transport '0' after 5 ns;


is translated into

test <= transport '0', '1' after 3 ns; -- '0' because of default
expression
test <= transport '0', '0' after 5 ns;

So after 3 ns there are actually two active drivers; one which drives
'0' and one which drives '1'.

so this explains the problem.

so long
lundril

 
Reply With Quote
 
Mike Treseler
Guest
Posts: n/a
 
      05-08-2006
(E-Mail Removed) wrote:
> Arg, okay I found the paragraph which explains this:

.. . .
> So after 3 ns there are actually two active drivers; one which drives
> '0' and one which drives '1'.


There two active drivers at time zero also.
The resolution function determines the value.
Whenever one drives '1' and the other drives '0'
the result is 'X'.

-- Mike Treseler

 
Reply With Quote
 
Marcus Harnisch
Guest
Posts: n/a
 
      05-09-2006
Marcus Harnisch <(E-Mail Removed)> writes:
> Every signal driver performs the following steps upon execution:
>
> - Delete all currently scheduled events
>
> - Add own waveform
> [...]


Which was, as you correctly pointed out, lundril, utter rubbish. What
I described is valid only for consecutive assignments.

Sorry about that,
Marcus
 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
difference between inertial and transport delay surpriya.7 VHDL 2 03-25-2009 08:57 AM
Calculating propagation delay & transmission delay Stone Cisco 1 09-27-2006 06:26 PM
want to replace a read only cd transport with read / write transport larya Computer Support 7 09-11-2006 10:21 PM
Transport and inertial delay , resolution fns kitcha VHDL 3 11-24-2005 02:09 AM
CDO Question: transport failed to connect to the server Lori McDonald ASP .Net 0 02-16-2004 08:09 PM



Advertisments