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VHDL - Array's of files

 
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Old 06-23-2005, 12:52 PM   #1
Default Array's of files


Hi all

Im trying to create a selection of files for a testbench, but the
compiler is failing on the brackets. I tried the equivalent setup with
a loop statement previously and that failed as well. Is there an easy
way, or will I just need to define unique file names and create a
explicit case statement in my code instead of an indexing signal??

The other option would be to have one bigger 'ReadF.txt' file, but then
I lose flexibility for other tests...

Thanks

Andrew

OUTPUT_WORD : process (gsr, sys_clk)
variable VEC_WR_LINE : line;
variable VEC_RD_LINE : line;
file VEC_WR_FILE : text open write_mode is "WriteF.txt";
file VEC_RD_FILE(0) : text open read_mode is "ReadF.txt";
file VEC_RD_FILE(1) : text open read_mode is "ReadF.txt";
file VEC_RD_FILE(2) : text open read_mode is "ReadF.txt";
file VEC_RD_FILE(3) : text open read_mode is "ReadF.txt";
file VEC_RD_FILE(4) : text open read_mode is "ReadF.txt";
variable file_rd_bit_vec : bit_vector (15 downto 0);
begin



dwerdna
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Old 06-23-2005, 02:57 PM   #2
Mike Treseler
 
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Default Re: Array's of files
dwerdna wrote:

> I'm trying to create a selection of files for a testbench, but the
> compiler is failing on the brackets.


Declare an array of files type and an instance, something like:
type selection_t is array(1 to 4) of file;
variable vec_rd_file : selection_t;
file vec_rd_file(1) : text open READ_MODE is "ReadF1.txt";
file vec_rd_file(2) : text open READ_MODE is "ReadF2.txt";

-- Mike Treseler


Mike Treseler
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Old 06-23-2005, 04:07 PM   #3
john Doef
 
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Default Re: Array's of files


dwerdna a écrit :
> Hi all
>
> Im trying to create a selection of files for a testbench, but the
> compiler is failing on the brackets. I tried the equivalent setup with
> a loop statement previously and that failed as well. Is there an easy
> way, or will I just need to define unique file names and create a
> explicit case statement in my code instead of an indexing signal??
>
> The other option would be to have one bigger 'ReadF.txt' file, but then
> I lose flexibility for other tests...
>
> Thanks
>
> Andrew
>
> OUTPUT_WORD : process (gsr, sys_clk)
> variable VEC_WR_LINE : line;
> variable VEC_RD_LINE : line;
> file VEC_WR_FILE : text open write_mode is "WriteF.txt";
> file VEC_RD_FILE(0) : text open read_mode is "ReadF.txt";
> file VEC_RD_FILE(1) : text open read_mode is "ReadF.txt";
> file VEC_RD_FILE(2) : text open read_mode is "ReadF.txt";
> file VEC_RD_FILE(3) : text open read_mode is "ReadF.txt";
> file VEC_RD_FILE(4) : text open read_mode is "ReadF.txt";
> variable file_rd_bit_vec : bit_vector (15 downto 0);
> begin


VHDL does not allow you to declare or use array of files.
I don't really understand what you want to do. Why do you want to open
a file
5 times.
If you want to select a file, do it:

constant my_filename : string := filename_chooser;
file vec_rd_file : text open read_mode is my_filename;

or because you are using VHDL-93, try:
file vec_rd_file : text;
....
file_open (vec_rd_file, "xxx.txt");

John.



john Doef
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Old 06-23-2005, 04:43 PM   #4
Mike Treseler
 
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Default Re: Array's of files (illegal)
Mike Treseler wrote:

> Declare an array of files type and an instance, something like:
> type selection_t is array(1 to 4) of file;
> variable vec_rd_file : selection_t;
> file vec_rd_file(1) : text open READ_MODE is "ReadF1.txt";

^
syntax error

Sorry, I got it wrong.
Arrays of files are illegal.

-- Mike Treseler


Mike Treseler
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Old 06-24-2005, 09:01 AM   #5
dwerdna
 
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Default Re: Array's of files (illegal)
Hi all

Thanks for your comments

I have a simple file which I use to simulate memory. I want to expand
how many reads I do to that memory without increasing the file size.
There is no particular reason in not increasing the file size, except I
use the smaller file in other places. I therefore wanted to open an
array of these files and have a pointer on which file to read from
(exhaust one, and move onto the next).

Thanks

Andrew



dwerdna
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