Velocity Reviews > VHDL > comparing the contents of memory

# comparing the contents of memory

srinukasam
Guest
Posts: n/a

 06-22-2005
hi to all
i designed a memory of 64 bit width( each memory location). and i want to
read that loaction by 16 bit (0-15 bit first then 16-31 ...)or after
reading the 64 bit i want to divide that by 16 bit each.after that i want
to comapre this 16 bit data with input data(16 bit).
thank you for reading my problem.
please reply , if you knows the solution.
bye

Ralf Hildebrandt
Guest
Posts: n/a

 06-22-2005
srinukasam wrote:

> i designed a memory of 64 bit width( each memory location). and i want to
> read that loaction by 16 bit (0-15 bit first then 16-31 ...)

Hmm ... a 64 bit memory that is accesses with a 16 bit wide bus seems to
me beeing just a 16 bit memory. You as the designer can have in mind,
that 4 words are logically grouped to a 64 bit value, but for hardware
it is just a 16 bit memeory.

-----------------------------------------------------
address 0x0 : 16 bit word A1 |
address 0x1 : 16 bit word A2 | group of words
address 0x2 : 16 bit word A3 | for 64 bit value A
address 0x3 : 16 bit word A4 |
-----------------------------------------------------
address 0x4 : 16 bit word B1 |
address 0x5 : 16 bit word B2 | group of words
address 0x6 : 16 bit word B3 | for 64 bit value B
address 0x7 : 16 bit word B4 |
-----------------------------------------------------

Did I understand you right?

> or after
> reading the 64 bit i want to divide that by 16 bit each.

Do you want to divide the 64 bit wide number by a 16 bit wide number or
do you want to divide the 64 bit wide number by 16?

Dividing by 16 is just shifting 4 bits to the right. Dividing by a 16
bit wide number is quite complex in hardware.

If you want to divide your 64 bit dividend by a known divisor, just
multiply the dividend by the inverse of the divisor which is much easier.

What about the fractions? Do you need floating point precision or is
fixed point precision suitable?

> after that i want
> to comapre this 16 bit data with input data(16 bit).

if (signal_A = signal_B) then
-- do some stuff
-- ... and so on

Ralf

srinukasam
Guest
Posts: n/a

 06-23-2005
hi
sorry , i explained my problem in a wrong way.
i read memory of 64 bit width , after reading i want to seperate that
word(64 bit) in to 16 bit each( so 4 words) , then i need to compare this
16 bit ( 4 words) with input 16 bit word( 4 times).
please reply a solution fo r this.
iam very thankful to all.
bye

srinukasam
Guest
Posts: n/a

 06-23-2005
hi
i written a code for parametrisable multiplexer .but it having problem at
my position(array)..i know its wrong that i declared it as integer .but
what is the alternate for taht array.iam using generate statement.

generic ( k :integer :=8; --input signal width
x :integer :=3; -- control signal width
r,v :integer :=3); -- no of output signals(r),no.of control
signals (V)

port(input:in std_logic_vector( k-1 downto 0);
ctrl: in ctrl_gen;
z: OUT out_gen);
END ENTITY mux_gen;

ARCHITECTURE mux_gen_beh OF mux_gen IS
BEGIN
type position is array(0 to r-1) of integer; --here is the problem in
declaration

type temp1 is array( 0 to r-1) of std_logic;
begin
if clk'event and clk='1' then
ge:for i in 0 to r-1 generate
position(i) <= vect_to_int(ctrl(i)); ---problem here also

temp1(i) <= input(position(i)+1);

z(i)<= temp1(i);

end generate ge;
end if;
end mux_gen_beh;

function vect_to_int(a :std_logic_vector(x-1 downto 0)) return integer is

variable result :integer:=0;
variable int_res : integer:=0;
begin
for i in 0 to x-1 loop
if a(i) = '1' then
int_res:=2**i;
--int_res := unsigned(a(i))*(2**i);
result := result+int_res;
end if;
end loop;
return result;

end vect_to_int;

info_
Guest
Posts: n/a

 06-23-2005
What kind of code is this ? VHDL ?
Did you just compile it ???

srinukasam wrote:

> hi
> i written a code for parametrisable multiplexer .but it having problem at
> my position(array)..i know its wrong that i declared it as integer .but
> what is the alternate for taht array.iam using generate statement.
> please reply what is the alternate
>
>
> generic ( k :integer :=8; --input signal width
> x :integer :=3; -- control signal width
> r,v :integer :=3); -- no of output signals(r),no.of control
> signals (V)
>
> port(input:in std_logic_vector( k-1 downto 0);
> ctrl: in ctrl_gen;
> z: OUT out_gen);
> END ENTITY mux_gen;
>
> ARCHITECTURE mux_gen_beh OF mux_gen IS
> BEGIN
> type position is array(0 to r-1) of integer; --here is the problem in
> declaration
>
> type temp1 is array( 0 to r-1) of std_logic;
> begin
> if clk'event and clk='1' then
> ge:for i in 0 to r-1 generate
> position(i) <= vect_to_int(ctrl(i)); ---problem here also
>
> temp1(i) <= input(position(i)+1);
>
> z(i)<= temp1(i);
>
> end generate ge;
> end if;
> end mux_gen_beh;
>
>
>
> function vect_to_int(a :std_logic_vector(x-1 downto 0)) return integer is
>
> variable result :integer:=0;
> variable int_res : integer:=0;
> begin
> for i in 0 to x-1 loop
> if a(i) = '1' then
> int_res:=2**i;
> --int_res := unsigned(a(i))*(2**i);
> result := result+int_res;
> end if;
> end loop;
> return result;
>
> end vect_to_int;
>

Ralf Hildebrandt
Guest
Posts: n/a

 06-23-2005
srinukasam wrote:

> i read memory of 64 bit width , after reading i want to seperate that
> word(64 bit) in to 16 bit each( so 4 words)

signal vector_64 : std_ulogic_vector(63 downto 0);
signal word1,word2,word3,word4 : std_ulogic_vector(15 downto 0);

word1<=vector_64(15 downto 0);
word2<=vector_64(31 downto 16);
word3<=vector_64(47 downto 32);
word4<=vector_64(63 downto 4;

Where is the problem?

> , then i need to compare this
> 16 bit ( 4 words) with input 16 bit word( 4 times).

signal equal1,equal2,equal3,equal4 : std_ulogic;

process(word1, input_16)
if (word1 = input_16) begin
equal1<='1';
else
equal1<='0';
end if;
end process;

process(word2, input_16)
if (word2 = input_16) begin
equal2<='1';
else
equal2<='0';
end if;

end process;

process(word3, input_16)
if (word3 = input_16) begin
equal3<='1';
else
equal3<='0';
end if;
end process;

equal4<='1' when (word4 = input_16) else '0'; -- less to type, but same solution

Note, that this parallel solution results in 64 XOR-gates and a couple of OR-gates. You
may also do these tests serially to save area.

But if I understood your problem right - where is the problem? Selecting some bits out of
a vector is one of the most easiest stuff VHDL offers and comparing some values is nothing
more than plain combinational logic.
I suggest you to read a VHDL book, before starting. For me "HDL Chip Design" was a good
book for learing VHDL - and Verilog, too.

Ralf