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hi,
i've found that + operator doesn't work with std_logic values.
it works only with std_logic_vector.
i've checked if a,b & c are std_logic values than
c <= a + b; gives compile time errors.
why it happens?
cann't we use + operator with single std_logic values.
regards
jitendra.

jiten wrote:
> hi,
> i've found that + operator doesn't work with std_logic values.
> it works only with std_logic_vector.

Not even. You'd need Synopsys' std_logic_unsigned (eg) which use
is deprecated (with reasons) against numeric_std which requires
signed or unsigned types.

> i've checked if a,b & c are std_logic values than
> c <= a + b; gives compile time errors.
> why it happens?
> cann't we use + operator with single std_logic values.
> regards
> jitendra.
>

Lots of things the VHDL Jedi needs to learn

Unlike Verilog, VHDL is strongly typed.

Btw, I think a one bit adder is just an xor, so
c <= a xor b;
is probably what you're looking for.
Alternatively, you could use one-bit vectors (0 downto 0).

Bert Cuzeau

The "+" operator works with std_logic_values but the addtions of two
single bit makes the result a vector. so you've got type mismatch
there. declaring your "c" as std_logic_vector should make it fine.

Jiten,
I see that you have been trying to get your vhdl right by posting to
this newsgroup. Thats fine, but, I feel you have got to know about
digital structures out of a good book like say, Mano before you try
describing hardware in HDLs. It dosent help by just learning how to
write vhdl. you need a good understanding of logic before you can apply
it effectively.