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VHDL - Where is the bug?

 
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Old 06-21-2005, 05:55 PM   #1
Default Where is the bug?


FUNCTION AN( A : std_logic_vector ) RETURN std_logic_vector IS
ALIAS result : std_logic_vector ( 1 TO A'LENGTH ) IS A;
BEGIN
RETURN result; -- 00000001
END ;
constant A1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
constant C1 : STD_LOGIC_VECTOR := AN(A1); -- UWUXUUUU


the weird value UWUXUUUU is assigned to C1 constant instead of the returned
00000001. Where is the bug?




valentin tihomirov
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Old 06-21-2005, 06:17 PM   #2
Jonathan Bromley
 
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Default Re: Where is the bug?
On Tue, 21 Jun 2005 19:55:52 +0300, "valentin tihomirov"
<> wrote:

> FUNCTION AN( A : std_logic_vector ) RETURN std_logic_vector IS
> ALIAS result : std_logic_vector ( 1 TO A'LENGTH ) IS A;
> BEGIN
> RETURN result; -- 00000001
> END ;
> constant A1 : STD_LOGIC_VECTOR (7 downto 0) := "00000001";
> constant C1 : STD_LOGIC_VECTOR := AN(A1); -- UWUXUUUU
>
>
>the weird value UWUXUUUU is assigned to C1 constant instead of the returned
>00000001. Where is the bug?


No bug when I run it here. What's the context, and what tools?
--
Jonathan Bromley, Consultant

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Jonathan Bromley
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Old 06-21-2005, 07:27 PM   #3
valentin tihomirov
 
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Default Re: Where is the bug?
Here is the full code. Do you feel anything bad what could cause garbage
assignment to r2 while XXX returns a robust vector? I gonna report the tool
vendor.

library ieee;
use ieee.std_logic_1164.all;

entity BUG is
end BUG;

architecture BUG of BUG is
subtype BYTE is std_logic_vector (7 downto 0);
function "and"(constant l, r: in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR
is
function XXX(constant x: in STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return x; -- returns 11111
end;

-- UUUXWUUU is assigned
constant r2: STD_LOGIC_VECTOR := XXX("1111111");

begin
assert false
report "bugbug, r2 sucks"
severity note;
return l;
end;
begin

process
variable KEY: BYTE;
begin
key := "11111111" and x"01";
wait;
end process;

end BUG;




valentin tihomirov
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