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Post Translate Timing

 
 
yaseenzaidi@NETZERO.com
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      06-21-2005
Greetings,

I have a situation where Post Translate timing is significantly
different from behavioral/RTL simulation. I am not not speaking of
simple delays, the outputs/data are different than what they should be.


What is interesting is that the design works on the FPGA board.
I implemented a serial port in loopback mode in Xilinx, if I type a
character on Hyperterm I get the same returned from the FPGA.

I have set timing constraints but to no effect.

YZ

 
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Mike Treseler
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      06-21-2005
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:

> I have a situation where Post Translate timing is significantly
> different from behavioral/RTL simulation. I am not not speaking of
> simple delays, the outputs/data are different than what they should be.


Gate level sims are more complex than functional.
I expect your error is here.
However, if static timing is ok and the thing works
I wouldn't bother performing or debuging a gate sim.

-- Mike Treseler
 
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Vladislav Muravin
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      06-21-2005
This is common to have a gate-level problems whi;le the design is working on
the board.
If your design is not high-speed and your statis timing analysis is alright,
then running gate-level simulation is really almost meaningless, as this is
FPGA and not ASIC.

Vladislav

<(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
> Greetings,
>
> I have a situation where Post Translate timing is significantly
> different from behavioral/RTL simulation. I am not not speaking of
> simple delays, the outputs/data are different than what they should be.
>
>
> What is interesting is that the design works on the FPGA board.
> I implemented a serial port in loopback mode in Xilinx, if I type a
> character on Hyperterm I get the same returned from the FPGA.
>
> I have set timing constraints but to no effect.
>
> YZ
>



 
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Bert Cuzeau
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      06-22-2005
(E-Mail Removed) wrote:

> Greetings,
>
> I have a situation where Post Translate timing is significantly
> different from behavioral/RTL simulation. I am not not speaking of
> simple delays, the outputs/data are different than what they should be.
>
>
> What is interesting is that the design works on the FPGA board.
> I implemented a serial port in loopback mode in Xilinx, if I type a
> character on Hyperterm I get the same returned from the FPGA.
>
> I have set timing constraints but to no effect.
>
> YZ
>


In a real design where correctness matters, I wouldn't discard
this discrepancy without taking a closer look...

It could mean that your design does't work at worst case timing,
or it could hide some unwelcome asynchronous feature or incorrect
clock domain crossing etc...
A couple of characters through Hyperterminal is not a good "proof"
of design correctness.
If you use Quartus, you could take a look at the Design Assistant's
report, or investigate the problem a bit further.
A potential error might create havoc much later.

Bert Cuzeau

 
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