N-Input Gate Using Loop or Generate

I have been thinking of making generic gates for a library. These
would be single N-input gates. A gate is easy enough to code, but I
have not been able think of a way to do this using a generate or other
loop statement so that a single component declaration would work for
each gate type (and, or, etc.). An instantiated component would look
like this (I might put some extras in to set polarity of each input and
the output):

and_gate_1 : and_gate
generic map( N => 3 ) -- positve
port map( input => gate_1_in, -- std_logic_vector(0 to N-1)
output => gate_1_out ); -- std_logic


Suggestions?

Best regards,

Charles

charles.elias@wpafb.af.mil

On 17 Jun 2005 05:30:38 -0700, wrote:

>I have been thinking of making generic gates for a library. These
>would be single N-input gates. A gate is easy enough to code, but I
>have not been able think of a way to do this using a generate or other
>loop statement so that a single component declaration would work for
>each gate type (and, or, etc.). An instantiated component would look
>like this (I might put some extras in to set polarity of each input and
>the output):
>
>and_gate_1 : and_gate
> generic map( N => 3 ) -- positve
> port map( input => gate_1_in, -- std_logic_vector(0 to N-1)
> output => gate_1_out ); -- std_logic
>

Why the generic? How about an unconstrained input port? Then
you don't need to specify N, but simply connect up any old vector
to the input and the gate will automatically re-size itself:

entity poly_and_gate is
port (A: in std_logic_vector; Y: out std_logic);
end;
architecture P of poly_and_gate is
begin
process (A)
variable result: std_logic;
begin
result := '1';
for i in A'range loop
result := result and A(i);
end loop;
Y <= result;
end process;
end;

Or, probably even better, a function with an unconstrained
input parameter.

Verilog, of course, has the reduction operators that do the
same thing, to say nothing of its primitive gates.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Jonathan Bromley

Jonathan,

Excellent idea! Replies like yours are what makes this such a good
group.

Thank you,

Charles

charles.elias@wpafb.af.mil

On 17 Jun 2005 07:38:48 -0700, wrote:

Charles,

>Excellent idea!

Thanks for the nice reply, but I forgot to mention the bad news:
some synthesis tools don't understand unconstrained ports -
mostly the big-bucks ASIC tools whose origins are firmly rooted
in Verilog, which has no such concept. For these tools you must
either use a function with an unconstrained parameter, or supply
a generic in the way you suggested.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Jonathan Bromley

Charles,
The vhdl-200x working group has a proposal for exending standard
logic operators as unary reduction operators. It would work as follows:

signal Y : std_logic ;
signal A : std_logic_vector(7 downto 0) ;

Y <= and A ;

or more exciting:

EvenParity <= xor Data ;

Cheers,
Jim


> I have been thinking of making generic gates for a library. These
> would be single N-input gates. A gate is easy enough to code, but I
> have not been able think of a way to do this using a generate or other
> loop statement so that a single component declaration would work for
> each gate type (and, or, etc.). An instantiated component would look
> like this (I might put some extras in to set polarity of each input and
> the output):
>
> and_gate_1 : and_gate
> generic map( N => 3 ) -- positve
> port map( input => gate_1_in, -- std_logic_vector(0 to N-1)
> output => gate_1_out ); -- std_logic
>
>
> Suggestions?
>
> Best regards,
>
> Charles
>


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training private.php?do=newpm&u=
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

Jim Lewis

> On 17 Jun 2005 05:30:38 -0700, wrote:
>
>
>>I have been thinking of making generic gates for a library. These
>>would be single N-input gates. A gate is easy enough to code, but I
>>have not been able think of a way to do this using a generate or other
>>loop statement so that a single component declaration would work for
>>each gate type (and, or, etc.). An instantiated component would look
>>like this (I might put some extras in to set polarity of each input and
>>the output):
>>
>>and_gate_1 : and_gate
>> generic map( N => 3 ) -- positve
>> port map( input => gate_1_in, -- std_logic_vector(0 to N-1)
>> output => gate_1_out ); -- std_logic
>>
>
>
> Why the generic? How about an unconstrained input port? Then
> you don't need to specify N, but simply connect up any old vector
> to the input and the gate will automatically re-size itself:
>
> entity poly_and_gate is
> port (A: in std_logic_vector; Y: out std_logic);
> end;
> architecture P of poly_and_gate is
> begin
> process (A)
> variable result: std_logic;
> begin
> result := '1';
> for i in A'range loop
> result := result and A(i);
> end loop;
> Y <= result;
> end process;
> end;
>
> Or, probably even better, a function with an unconstrained
> input parameter.
>
> Verilog, of course, has the reduction operators that do the
> same thing, to say nothing of its primitive gates.

As Jonathan mentioned (later thread), to make it synthesizable
you need a generic, but its addition is trivial (sorry for starting
in the middle, but the code I want to copy from is here):


entity poly_and_gate is
generic ( N : integer );
port ( A : in std_logic_vector(N-1 downto 0); Y: out std_logic);
end;

Then to parameterize your instantiation use 'length:
and_gate_1 : and_gate
generic map( N => gate_1_in'length ) -- positve
port map( input => gate_1_in, -- std_logic_vector(0 to N-1)
output => gate_1_out ); -- std_logic

Cheers,
Jim
P.S.
Don't forget as I mentioned in my earlier post, we plan to
add this sometime during one of the VHDL-200X revisions.
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training private.php?do=newpm&u=
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

Jim Lewis

Thanks, everyone for your help. I thought you might like to see an
example of what I actually put in my library:

--A_pol sets the "polarity" of each input; if A_pol( i ) = '0' then
A(i) is low assertive, if A_pol(i) = '1' then A(i) is high assertive.
--In a similar manner, Y_pol sets the polarity of the output Y.

entity or_gate is
generic ( N : positive );
port ( A_pol : in std_logic_vector( N - 1 downto 0 ) := ( others =>
'1' );
Y_pol : in std_logic := '1';
A : in std_logic_vector( N - 1 downto 0 );
Y : out std_logic
);
end;

architecture P of or_gate is
begin
process ( A, A_pol, Y_pol )
variable result: std_logic;
begin
result := '0';
for i in A'range loop
result := result or ( ( not A_pol( i ) ) xor A( i ) );
end loop;
Y <= ( not Y_pol ) xor result;
end process;
end;
----------------------------------------------------------------------------------------
Charles

charles.elias@wpafb.af.mil