FIFO simulation

Hi,

I have generated a FIFO with output registers and one without
output registers. (Altera QuartusII MegaWizardManager)

And yet when simulating both in Modelsim(functional simulation)I get
the same result: The data appear on the output of the FIFO immediately
after asserting the rdreq.

Any ideas what could be wrong ?

Here is my testbench code:

ibrary ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity tb_fifo_test_unregistered is
end tb_fifo_test_unregistered;


architecture testbench of tb_fifo_test_unregistered is

component fifo_test_unregistered
port ( Data : in std_logic_vector(8 downto 0);
Wrreq : in std_logic;
Rdreq : in std_logic;
Clock : in std_logic;
Aclr : in std_logic;
Q : out std_logic_vector(8 downto 0)
);

end component;

signal t_data : std_logic_vector(8 downto 0);
signal t_wrreq : std_logic;
signal t_rdreq : std_logic;
signal t_clock : std_logic;
signal t_clock2 : std_logic;
signal t_aclr : std_logic;
signal t_q : std_logic_vector(8 downto 0);

begin

uut : fifo_test_unregistered
port map ( Data => t_data,
Wrreq => t_wrreq,
Rdreq => t_rdreq,
Clock => t_clock2,
Aclr => t_aclr,
Q => t_q
);

process
begin
t_clock <= '1'; wait for 5.5 ns;
t_clock <= '0'; wait for 5.5 ns;
end process;

process
begin
t_clock2 <= '0'; wait for 5.5 ns;
t_clock2 <= '1'; wait for 5.5 ns;
end process;



process
begin
t_aclr <= '1', '0' after 103 ns;
wait;
end process;



process
begin
t_data <= (others => '0');
t_wrreq <= '0';
t_rdreq <= '0';

for i in 0 to 40 loop
wait until rising_edge(t_clock);
end loop;

for i in 0 to 31 loop
wait until rising_edge(t_clock);
t_wrreq <= '1';
t_data <= conv_std_logic_vector(i+1, 9);
end loop;

t_wrreq <= '0';

for i in 0 to 10 loop
wait until rising_edge(t_clock);
end loop;

for i in 0 to 31 loop
wait until rising_edge(t_clock);
t_rdreq <= '1';
wait until rising_edge(t_clock);
t_rdreq <= '0';
wait until rising_edge(t_clock);
end loop;
t_rdreq <= '0';

wait;
end process;


end testbench;

ALuPin@web.de

Nothing is wrong with the test bench but you have not put the
registered fifo code here. cant make out anything without the rtl.

Neo

Here is the code for registered one:

LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;

ENTITY fifo_test_registered IS
PORT
(
data : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
wrreq : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END fifo_test_registered;


ARCHITECTURE SYN OF fifo_test_registered IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);



COMPONENT scfifo
GENERIC (
lpm_width : NATURAL;
lpm_numwords : NATURAL;
lpm_widthu : NATURAL;
intended_device_family : STRING;
lpm_type : STRING;
lpm_showahead : STRING;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING;
add_ram_output_register : STRING
);
PORT (
rdreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;

BEGIN
q <= sub_wire0(8 DOWNTO 0);

scfifo_component : scfifo
GENERIC MAP (
lpm_width => 9,
lpm_numwords => 32,
lpm_widthu => 5,
intended_device_family => "Cyclone",
lpm_type => "scfifo",
lpm_showahead => "OFF",
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON",
add_ram_output_register => "ON"
)
PORT MAP (
rdreq => rdreq,
aclr => aclr,
clock => clock,
wrreq => wrreq,
data => data,
q => sub_wire0
);
END SYN;




And here is the code for the non-registered one:





LIBRARY ieee;
USE ieee.std_logic_1164.all;

LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;

ENTITY fifo_test_unregistered IS
PORT
(
data : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
wrreq : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END fifo_test_unregistered;


ARCHITECTURE SYN OF fifo_test_unregistered IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (8 DOWNTO 0);



COMPONENT scfifo
GENERIC (
lpm_width : NATURAL;
lpm_numwords : NATURAL;
lpm_widthu : NATURAL;
intended_device_family : STRING;
lpm_type : STRING;
lpm_showahead : STRING;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING;
add_ram_output_register : STRING
);
PORT (
rdreq : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
wrreq : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (8 DOWNTO 0)
);
END COMPONENT;

BEGIN
q <= sub_wire0(8 DOWNTO 0);

scfifo_component : scfifo
GENERIC MAP (
lpm_width => 9,
lpm_numwords => 32,
lpm_widthu => 5,
intended_device_family => "Cyclone",
lpm_type => "scfifo",
lpm_showahead => "OFF",
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON",
add_ram_output_register => "OFF"
)
PORT MAP (
rdreq => rdreq,
aclr => aclr,
clock => clock,
wrreq => wrreq,
data => data,
q => sub_wire0
);



END SYN;

ALuPin@web.de

Well, its a macro so cant do much. try checking out the attributes of
the macro. But do you mean the output is available in the same cycle
the signal "rdreq" is aaeerted?

Neo

Yes, in both simulations.

Of course I have instantiated "fifo_test_registered" in my testbench
for the
registered version.

Rgds
André

ALuPin@web.de

Have you checked the documentation waveform that Quartus II
Megawizzard does generate for you to illustrate the behavior
of the generated macro ?

Simulating is still definitely a good idea...
however, I think you are changing rdreq just at the clock's rising edge,
which might be legit if you don't have any delta delay (which is hard
to assess in a macro model) but which makes the waveform harder to
interpret anyway.
I suggest you change your inputs at the clock's inactive (falling) edge.

Bert Cuzeau

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