component port mapping

Hi,
I just want to know if I missed something...
If you have a toplevel entity with say a bus of single std_logic
signals of inout mode and want to use this within a component, you
can't really combine the signals to a std_logic_vector... right? That
means you have to use the single inout signals on the component as well
and use the toplevel entity signal names as actuals for the component
instantiation.
Two reasons:
- if you use a signal assignment to map the signals into a vector, its
only one direction...
- u can't use array aggregates as actuals, beause they're not locally
static, so a concatenation of type data => d4 & d3 & d2 & d1 would
not work...

Do you guys agree or did I miss a possibility?
Cheers
Andreas

ajahn

what about this 'struct' solution: no in, no out, no hassle!

type data_t is record
d1 : std_logic;
d2 : std_logic;
d3 : std_logic;
d4 : std_logic;
end record;

entity MY_ENT is
....
data: inout data_t;
....

ajahn wrote:
> Hi,
> I just want to know if I missed something...
> If you have a toplevel entity with say a bus of single std_logic
> signals of inout mode and want to use this within a component, you
> can't really combine the signals to a std_logic_vector... right? That
> means you have to use the single inout signals on the component as well
> and use the toplevel entity signal names as actuals for the component
> instantiation.
> Two reasons:
> - if you use a signal assignment to map the signals into a vector, its
> only one direction...
> - u can't use array aggregates as actuals, beause they're not locally
> static, so a concatenation of type data => d4 & d3 & d2 & d1 would
> not work...

no, but you workaround:
signal data_in: std_logic_vector(3 downto 0);
signal data_out: std_logic_vector(3 downto 0);
begin
....
data_out <= d4 & d3 & d2 & d1;
din1 <= data_in(0);
....
--instanciation:
....
data_out=>data_out,
data_in=>data_in,
....


I prefer the 'record' solution, but some tools don't seem to !

>
> Do you guys agree or did I miss a possibility?
> Cheers
> Andreas
>

Stephane

ajahn wrote:

> If you have a toplevel entity with say a bus of single std_logic
> signals of inout mode and want to use this within a component, you
> can't really combine the signals to a std_logic_vector... right?

> - if you use a signal assignment to map the signals into a vector, its
> only one direction...
> - u can't use array aggregates as actuals, beause they're not locally
> static, so a concatenation of type data => d4 & d3 & d2 & d1 would
> not work...

Using ports of type inout is often not a good way in deeper hierarchy of
the design. Split every inout signals into one signal for input and one
for output direction.

Ralf

Ralf Hildebrandt