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Jan Decaluwe schrieb:
> - it shows how you can use non-synthesizable constructs in MyHDL
> and still get synthesizable Verilog out of it (Really!)

I heard a research talk on a GI workshop that talked about using simple
XSLT translations to make common unsynthesizable VHDL code synthesizable.

IMHO it is embarrassing that a 2006 compiler cannot synthesize

if rising_edge(clk) and enable='1' then...

Kolja Sulimma