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Hi,

I'm currently getting a strange message from my testbench output that
says

"Error: Master Selection : Test case 5 failed. Master bit was '1' but
should have been '1'"

This is generated using the following:
assert ((DATA_BUS(master_bit)) = (this_case(0)));
report "Master Selection : Test case " & integer'image(I) & " failed.
Master bit was " & std_logic'image(DATA_BUS(master_bit)) & " but should
have been " & std_logic'image(this_case(0))
severity error;

Why is this?
master_bit is an integer, DATA_BUS is a 16 bit std_logic_vector input
to my procedure and this_case is a 4-bit std_logic_vector

What I don't understand is why the comparison after the assert is false
when printing the two bits out in the report they look the same.

All suggestions appreciated

Steve

Hi Steve,

this a trap of VHDL, because the assert statement tests on false Condition!
You can write :

assert NOT(((DATA_BUS(master_bit)) = (this_case(0))));
^
or assert ((DATA_BUS(master_bit)) /= (this_case(0)));
^

regards,

Steffen

Steve J wrote:
> Hi,
>
> I'm currently getting a strange message from my testbench output that
> says
>
> "Error: Master Selection : Test case 5 failed. Master bit was '1' but
> should have been '1'"
>
> This is generated using the following:
> assert ((DATA_BUS(master_bit)) = (this_case(0)));
> report "Master Selection : Test case " & integer'image(I) & " failed.
> Master bit was " & std_logic'image(DATA_BUS(master_bit)) & " but should
> have been " & std_logic'image(this_case(0))
> severity error;
>
> Why is this?
> master_bit is an integer, DATA_BUS is a 16 bit std_logic_vector input
> to my procedure and this_case is a 4-bit std_logic_vector
>
> What I don't understand is why the comparison after the assert is false
> when printing the two bits out in the report they look the same.
>
> All suggestions appreciated
>
> Steve
>

I appreciate that assert reports an error on a false condition. That's
not what is confusing me as I've tried adding a not and the same thing
happens.

In the report statement I'm using the 'image to output the value of the
two sides of the comparison.

What I don't understand is why if both sides of the '=' are the same,
why is the rest of the report/severity bit being triggered. Surely '1'
= '1' is true and hence I wouldn't get a message.

Steve

Steffen Netz wrote:
> Hi Steve,
>
> this a trap of VHDL, because the assert statement tests on false Condition!
> You can write :
>
> assert NOT(((DATA_BUS(master_bit)) = (this_case(0))));
> ^
> or assert ((DATA_BUS(master_bit)) /= (this_case(0)));
> ^
>
> regards,
>
> Steffen
>
> Steve J wrote:
> > Hi,
> >
> > I'm currently getting a strange message from my testbench output that
> > says
> >



> > "Error: Master Selection : Test case 5 failed. Master bit was '1' but
> > should have been '1'"
> >
> > This is generated using the following:
> > assert ((DATA_BUS(master_bit)) = (this_case(0)));
> > report "Master Selection : Test case " & integer'image(I) & " failed.
> > Master bit was " & std_logic'image(DATA_BUS(master_bit)) & " but should
> > have been " & std_logic'image(this_case(0))
> > severity error;
> >
> > Why is this?
> > master_bit is an integer, DATA_BUS is a 16 bit std_logic_vector input
> > to my procedure and this_case is a 4-bit std_logic_vector
> >
> > What I don't understand is why the comparison after the assert is false
> > when printing the two bits out in the report they look the same.
> >
> > All suggestions appreciated
> >
> > Steve
> >

I've replaced the statement causing me problems with

assert true;
report "......

and I still get the error messages.

Why would an assert statement always trigger? The assert is in a
procedure in a package. Would that cause problems?

TIA

Steve

Hey,

assert rises the message if the condition is "true" !!!

assert true
report "I'm here"

gives I'm here

assert false
report "I'm here"

gives -
( Nothing ) !!!

Steffen

Steve J wrote:
> I appreciate that assert reports an error on a false condition. That's
> not what is confusing me as I've tried adding a not and the same thing
> happens.
>
> In the report statement I'm using the 'image to output the value of the
> two sides of the comparison.
>
> What I don't understand is why if both sides of the '=' are the same,
> why is the rest of the report/severity bit being triggered. Surely '1'
> = '1' is true and hence I wouldn't get a message.
>
> Steve
>
> Steffen Netz wrote:
> > Hi Steve,
> >
> > this a trap of VHDL, because the assert statement tests on false Condition!
> > You can write :
> >
> > assert NOT(((DATA_BUS(master_bit)) = (this_case(0))));
> > ^
> > or assert ((DATA_BUS(master_bit)) /= (this_case(0)));
> > ^
> >
> > regards,
> >
> > Steffen
> >
> > Steve J wrote:
> > > Hi,
> > >
> > > I'm currently getting a strange message from my testbench output that
> > > says
> > >
>
>
>
> > > "Error: Master Selection : Test case 5 failed. Master bit was '1' but
> > > should have been '1'"
> > >
> > > This is generated using the following:
> > > assert ((DATA_BUS(master_bit)) = (this_case(0)));
> > > report "Master Selection : Test case " & integer'image(I) & " failed.
> > > Master bit was " & std_logic'image(DATA_BUS(master_bit)) & " but should
> > > have been " & std_logic'image(this_case(0))
> > > severity error;
> > >
> > > Why is this?
> > > master_bit is an integer, DATA_BUS is a 16 bit std_logic_vector input
> > > to my procedure and this_case is a 4-bit std_logic_vector
> > >
> > > What I don't understand is why the comparison after the assert is false
> > > when printing the two bits out in the report they look the same.
> > >
> > > All suggestions appreciated
> > >
> > > Steve
> > >
>

Steve J wrote:

> I've replaced the statement causing me problems with
>
> assert true;
> report "......
>
> and I still get the error messages.
>
> Why would an assert statement always trigger? The assert is in a
> procedure in a package. Would that cause problems?
>
> TIA
>
> Steve
>
Try removing the ; after assert. It executes a null command and the
report works always.

Mariusz,

Thanks for that. That appears to have solved it.
I'm surprised that isn't picked up by a syntax checker when I compile
the code.

Steffen,
Are you saying that in correct VHDL the error message is printed when
the condition is true? That's not what I've understood from other
sources.
http://www.acc-eda.com/vhdlref/refgu...statements.htm

Steve

....
>
> Steffen,
> Are you saying that in correct VHDL the error message is printed when
> the condition is true? That's not what I've understood from other
> sources.
> http://www.acc-eda.com/vhdlref/refgu...statements.htm
>
> Steve
>

I'm so stupid, that's when you have to work in Verilog for a while.
You are so right,
Sorry,

Steffen

Steve J wrote:

> Mariusz,
>
> Thanks for that. That appears to have solved it.
> I'm surprised that isn't picked up by a syntax checker when I compile
> the code.
>
> Steffen,
> Are you saying that in correct VHDL the error message is printed when
> the condition is true? That's not what I've understood from other
> sources.
> http://www.acc-eda.com/vhdlref/refgu...statements.htm
>
> Steve
>
Steve,

No compiler should complain. That's what LRM reads. All sections are
optional so assert alone is perfectly OK.

Mariusz

Hi,

"Steve J" <> wrote in message
news: ups.com...
> Mariusz,
>
> Thanks for that. That appears to have solved it.
> I'm surprised that isn't picked up by a syntax checker when I compile
> the code.

Perhaps you had a VHDL-93 mode turned ON (or is the default in your
compiler). report alone was allowed in VHDL-93, so if you wanted your
compiler to error out, use 87 - I wouldn't recommend that though.

--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned