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Warning:Xst:382 - Register A is equivalent to B

 
 
mag
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Posts: n/a
 
      05-19-2005
Hello

During synthesis of the code belove I have recieved two warnings:
----
Mapping all equations...
Building and optimizing final netlist ...
WARNING:Xst:382 - Register Mtrien_rx_minus is equivalent to Mtrien_rx_plus
Found area constraint ratio of 100 (+ 5) on block ways, actual ratio is 0.
WARNING:Xst:382 - Register Mtrien_rx_minus is equivalent to Mtrien_rx_plus
----

This code I wrote specially for 2-way signals "rx_minus" , "rx_plus" (that
is why it includes 2 processes). When the signal is = '1' then in the first
process those signals <= 'Z' and then they are inputs in the second process
(I did'n find better solution for this).

Ok, about the warning... Is the synthesis tool tying "rx_minus" , "rx_plus"
together? Both signals look the same but are not the same of course...

have you got any solution/explanation?

--- ---------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity ways is
port(
rst, clk : in std_logic;

rx_minus, rx_plus : inout std_logic;

Receiving_Data : in std_logic;
tx_minus_OUT, tx_plus_OUT : in std_logic;
rx_minus_input, rx_plus_input : out std_logic
);
end ways;

architecture arch_ways of ways is
begin
process(clk, Receiving_Data)
begin
if rising_edge(clk) then
if rst = '1' then

rx_minus <= 'Z';
rx_plus <= 'Z';

else

if Receiving_Data = '0' then
rx_minus <= tx_minus_OUT;
rx_plus <= tx_plus_OUT;

else

rx_minus <= 'Z';
rx_plus <= 'Z';

end if;
end if;
end if;

end process;

process(clk, Receiving_Data, rx_minus, rx_plus)
begin
if rising_edge(clk) then
if rst = '1' then
rx_minus_input <= '1';
rx_plus_input <= '1';
else

if Receiving_Data = '1' then
rx_minus_input <= rx_minus;
rx_plus_input <= rx_plus;
end if;
end if;
end if;
end process;

end architecture;


----

P.M
http://www.velocityreviews.com/forums/(E-Mail Removed)


 
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Andy Peters
Guest
Posts: n/a
 
      05-19-2005
mag wrote:
> Hello
>
> During synthesis of the code belove I have recieved two warnings:
> ----
> Mapping all equations...
> Building and optimizing final netlist ...
> WARNING:Xst:382 - Register Mtrien_rx_minus is equivalent to

Mtrien_rx_plus
> Found area constraint ratio of 100 (+ 5) on block ways, actual ratio

is 0.
> WARNING:Xst:382 - Register Mtrien_rx_minus is equivalent to

Mtrien_rx_plus
> ----
>
> This code I wrote specially for 2-way signals "rx_minus" , "rx_plus"

(that
> is why it includes 2 processes). When the signal is = '1' then in the

first
> process those signals <= 'Z' and then they are inputs in the second

process
> (I did'n find better solution for this).
>
> Ok, about the warning... Is the synthesis tool tying "rx_minus" ,

"rx_plus"
> together? Both signals look the same but are not the same of

course...
>
> have you got any solution/explanation?


> architecture arch_ways of ways is
> begin
> process(clk, Receiving_Data)


First -- why is Receiving_Data on your sensitivity list? Re-read the
synthesis tool documents.

> begin
> if rising_edge(clk) then
> if rst = '1' then
>
> rx_minus <= 'Z';
> rx_plus <= 'Z';


Think Hardware. What real flipflop lets you assign Hi-Z to its input
and then clock that through?

> else
>
> if Receiving_Data = '0' then
> rx_minus <= tx_minus_OUT;
> rx_plus <= tx_plus_OUT;
>
> else
>
> rx_minus <= 'Z';
> rx_plus <= 'Z';


Same comment about assigning Hi-Z here.

> end if;
> end if;
> end if;
>
> end process;
>
> process(clk, Receiving_Data, rx_minus, rx_plus)


Again, why the other stuff on the sensitivity list?

> begin
> if rising_edge(clk) then
> if rst = '1' then
> rx_minus_input <= '1';
> rx_plus_input <= '1';
> else
> if Receiving_Data = '1' then
> rx_minus_input <= rx_minus;
> rx_plus_input <= rx_plus;
> end if;
> end if;
> end if;
> end process;
>
> end architecture;


I think your problem is that you've confused the synthesis tool. You
need to come up with logic that creates output enables for your
bidirectional signals and use them in continuous assignments.

-a

 
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