The assign statement in verilog doesnt generate a module in design architect

aushitha

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04-30-2006

Hello
I have written a vhdl code for duplicating values.The problem is
in Mentor Graphic Design Architect the assign statement in Verilog
doesnt generate a schematic for my code.So I would like to know if
anybody faced such a problem and over came it.Is there anyother
statement in verilog which can be substituted for assign.Please let me
know.

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