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Synopsys vhdlsim (VHDL simulator)

 
 
gthorpe@ee.ryerson.ca
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      05-12-2005
Hi,

Unfortunately, there is no group I can find which can address questions
specific to synopsys-related tools like vhdlsim, so I post my question here.

Running some VHDL simulations using 'vhdlsim', I notice that the memory
requirements steadily increase to very large amounts with no end in sight
(however, another simulation of the same test bench but with different
parameters [such as the name of a data file, component speeds and clock speed]
does not seem to get very big [approaching 1GB]). Are there any general tips on
VHDL on how to reduce memory usage during simulation? Could this behaviour be
due to a simulator-specific feature/bug?
 
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Ralf Hildebrandt
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      05-12-2005
http://www.velocityreviews.com/forums/(E-Mail Removed) wrote:


> Running some VHDL simulations using 'vhdlsim', I notice that the memory
> requirements steadily increase to very large amounts with no end in sight

....
> Are there any general tips on
> VHDL on how to reduce memory usage during simulation?


One option may be to use unresolved data types such as
std_ulogic(_vector) instead of std_logic(_vector) as long as possible.
This has the advantage, that unwanted multiple drivers to one signal are
detected and it saves the resolution function.

But I don't have an idea how big are the differences...


Ralf
 
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Mike Treseler
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      05-12-2005
(E-Mail Removed) wrote:

> does not seem to get very big [approaching 1GB]). Are there any general tips on
> VHDL on how to reduce memory usage during simulation? Could this behaviour be
> due to a simulator-specific feature/bug?


http://groups-beta.google.com/groups...+ram_data_type

-- Mike Treseler
 
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