HEX to STD_LOGIC_VECTOR

Hi,

I am trying to simulate the following in Modelsim:


use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;

signal t_wraddress : std_logic_vector(14 downto 0);

begin
....

-- Instead of writing t_wraddress <= ("00010" & "0000100010");
-- or t_wraddress <= "000100000100010";
-- I want
-- some shorter expressions like

t_wraddress(14 downto 10) <= to_stdlogicvector(x"02");
t_wraddress(9 downto 0) <= to_stdlogicvector(x"22");


But I get the warning:
# Ambiguous parameter type to function 'to_stdlogicvector'.
# Expression is illegal VHDL-1993 but legal VHDL-1987.

So how can I change that ?

I tried to find some answers in different posts but...

Thank you for your help.

Rgds
André

ALuPin@web.de

-- Instead of writing t_wraddress <= ("00010" & "0000100010");
-- or t_wraddress <= "000100000100010";
-- I want
-- some shorter expressions like

t_wraddress(14 downto 10) <= to_stdlogicvector(x"02");
t_wraddress(9 downto 0) <= to_stdlogicvector(x"22");

X"AB03" is a legal 16 bit std_logic_vector.
You're trying to assign X"22", an 8 bit vector to a 10 bit vector.
You shouldn't need the conversion function.

Try something like t_wradress(9 downto 0) <= "00" & X"22"; -- If you want
10 bit assignment

Regards, Niv.

Niv

Try this. It should work.
Split your address into two parts: 3-bit part + 12-bit part
In 12-bit part you can easily assign a hex number, keep binary the rest.

Then
t_wraddress <= "000100000100010";

is the same as

t_wraddress <= "000" & x"822";

Good luck
stt


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Hi,

I am trying to simulate the following in Modelsim:


use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;

signal t_wraddress : std_logic_vector(14 downto 0);

begin
....

-- Instead of writing t_wraddress <= ("00010" & "0000100010");
-- or t_wraddress <= "000100000100010";
-- I want
-- some shorter expressions like

t_wraddress(14 downto 10) <= to_stdlogicvector(x"02");
t_wraddress(9 downto 0) <= to_stdlogicvector(x"22");


But I get the warning:
# Ambiguous parameter type to function 'to_stdlogicvector'.
# Expression is illegal VHDL-1993 but legal VHDL-1987.

So how can I change that ?

I tried to find some answers in different posts but...

Thank you for your help.

Rgds
André

Son Tran