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VHDL - Synopsys Design Analyzer in command prompt |
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#1 |
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Hi all,
This might not be the best group, but I was not able to find a better one... Does anyone knows whether it is possible to Synthesize a VHDL design with Synopsys design_analyzer from a UNIX command prompt. I need to do it remotely (SSH) without any graphical "connection"? Thanks in advance. /Kenneth Kenneth Brun Nielsen |
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#2 |
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Kenneth Brun Nielsen wrote:
> Hi all, > > This might not be the best group, but I was not able to find a better one... > > Does anyone knows whether it is possible to Synthesize a VHDL design with > Synopsys design_analyzer from a UNIX command prompt. I need to do it > remotely (SSH) without any graphical "connection"? I haven't used Synopsys for a few years, but it certainly used to be possible. In fact, it used to be the only way available to run it. The command was 'dc_shell' but, now that Synopsys uses Tcl as the script language, it might be something else (tcl_shell?). Synopsys' documentation is extensive so I'm sure the answer is in there. The help system was called SOLD (Synopsys OnLine Documentation) and it came on at least two separate CDs. -- Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com Tim Hubberstey |
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#3 |
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Hi
if you need to run design analyzer in command prompt you can use the following two commands depending on your scripts dc_shell -f script1 dc_shell-t -f script1.tcl (if you are using a tcl version of the synopsys script)..... One of the ways for you to obtain the dc script is save the transcript when you run the tool graphically..... basic dc script template looks like the following.. ************************************************** ************ read -format verilog sample_rtl.v uniquify ungroup -all -flatten compile -map_effort medium ungroup -all -flatten write -format verilog -hierarchy -output sample_netlist.v ************************************************** **************** topgun |
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#4 |
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"topgun" <> skrev i en meddelelse news: oups.com... > Hi > > if you need to run design analyzer in command prompt you can use the > following > two commands depending on your scripts > > dc_shell -f script1 > > dc_shell-t -f script1.tcl (if you are using a tcl version of the > synopsys script)..... > (...) Thank you very much, Topgun. You just saved my day! /Kenneth Kenneth Brun Nielsen |
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#5 |
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And another quick question: I used to report to the display - how do I
change that, so the report is printed to a file? I guess some parameter should be added to the "report"-command. TIA. /KBN Kenneth Brun Nielsen |
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#6 |
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"Kenneth Brun Nielsen" <news@_FJERNES_brun.dk> writes:
> And another quick question: I used to report to the display - how do I > change that, so the report is printed to a file? I guess some parameter > should be added to the "report"-command. report > filename ISTR that you can also use report >> filename to get data appended to the file. Kai -- Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk> Kai Harrekilde-Petersen |
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#7 |
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"Kai Harrekilde-Petersen" <> skrev i en meddelelse news:... > "Kenneth Brun Nielsen" <news@_FJERNES_brun.dk> writes: > >> And another quick question: I used to report to the display - how do I >> change that, so the report is printed to a file? I guess some parameter >> should be added to the "report"-command. > > report > filename > > ISTR that you can also use > > report >> filename > > to get data appended to the file. > > OK. That sounds feasible /KBN Kenneth Brun Nielsen |
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