parameterizing number of ports?

Hi

I want to make the following two simple 4-to-1 and 2-to-1 mux, into one
entity with parameterized ports.
I am trying generic statement, yet with no success --:
Could someone give some idea?
Thankyou


--------------------------------------------------------------
-- 4-to-1 Mux
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux_gate is
port ( SEL: in STD_LOGIC_VECTOR (1 downto 0);
A,B,C,D: in STD_LOGIC;
SIG: out STD_LOGIC);
end mux_gate;

architecture RTL of mux_gate is
begin
SEL_PROCESS: process (SEL,A,B,C,D)
begin
case SEL is
when "00" => SIG <= A;
when "01" => SIG <= B;
when "10" => SIG <= C;
when others => SIG <= D;
end case;
end process SEL_PROCESS;
end RTL;
---------------------------------------------------
-- 2-to-1 Mux
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity mux_gate is
port ( SEL: in STD_LOGIC;
A,B: in STD_LOGIC;
SIG: out STD_LOGIC);
end mux_gate;

architecture RTL of mux_gate is
begin
SEL_PROCESS: process (SEL,A,B)
begin
case SEL is
when "0" => SIG <= A;
when others => SIG <= B;
end case;
end process SEL_PROCESS;
end RTL;
-------------------------------------------------------

Pasacco

library ieee;
use ieee.std_logic_1164.all;
entity mux is
generic (w : natural:= 2); -- sel_width
port (sel : in std_logic_vector(w-1 downto 0);
d : in std_logic_vector(2**w-1 downto 0);
o : out std_logic);
end mux;

library ieee;
use ieee.numeric_std.all;
architecture bhv of mux is
begin
o <= d (to_integer(unsigned(sel)));
end bhv;

Egbert Molenkamp



"Pasacco" <> wrote in message
news: oups.com...
> Hi
>
> I want to make the following two simple 4-to-1 and 2-to-1 mux, into one
> entity with parameterized ports.
> I am trying generic statement, yet with no success --:
> Could someone give some idea?
> Thankyou
>
>
> --------------------------------------------------------------
> -- 4-to-1 Mux
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.std_logic_arith.all;
>
> entity mux_gate is
> port ( SEL: in STD_LOGIC_VECTOR (1 downto 0);
> A,B,C,D: in STD_LOGIC;
> SIG: out STD_LOGIC);
> end mux_gate;
>
> architecture RTL of mux_gate is
> begin
> SEL_PROCESS: process (SEL,A,B,C,D)
> begin
> case SEL is
> when "00" => SIG <= A;
> when "01" => SIG <= B;
> when "10" => SIG <= C;
> when others => SIG <= D;
> end case;
> end process SEL_PROCESS;
> end RTL;
> ---------------------------------------------------
> -- 2-to-1 Mux
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.std_logic_arith.all;
>
> entity mux_gate is
> port ( SEL: in STD_LOGIC;
> A,B: in STD_LOGIC;
> SIG: out STD_LOGIC);
> end mux_gate;
>
> architecture RTL of mux_gate is
> begin
> SEL_PROCESS: process (SEL,A,B)
> begin
> case SEL is
> when "0" => SIG <= A;
> when others => SIG <= B;
> end case;
> end process SEL_PROCESS;
> end RTL;
> -------------------------------------------------------
>

Egbert Molenkamp

Pasacco,
Perhaps you want to consider using functions to implement
this rather than an entity.

Cheers,
Jim


> Hi
>
> I want to make the following two simple 4-to-1 and 2-to-1 mux, into one
> entity with parameterized ports.
> I am trying generic statement, yet with no success --:
> Could someone give some idea?
> Thankyou
>
>
> --------------------------------------------------------------
> -- 4-to-1 Mux
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.std_logic_arith.all;
>
> entity mux_gate is
> port ( SEL: in STD_LOGIC_VECTOR (1 downto 0);
> A,B,C,D: in STD_LOGIC;
> SIG: out STD_LOGIC);
> end mux_gate;
>
> architecture RTL of mux_gate is
> begin
> SEL_PROCESS: process (SEL,A,B,C,D)
> begin
> case SEL is
> when "00" => SIG <= A;
> when "01" => SIG <= B;
> when "10" => SIG <= C;
> when others => SIG <= D;
> end case;
> end process SEL_PROCESS;
> end RTL;
> ---------------------------------------------------
> -- 2-to-1 Mux
> library IEEE;
> use IEEE.std_logic_1164.all;
> use IEEE.std_logic_arith.all;
>
> entity mux_gate is
> port ( SEL: in STD_LOGIC;
> A,B: in STD_LOGIC;
> SIG: out STD_LOGIC);
> end mux_gate;
>
> architecture RTL of mux_gate is
> begin
> SEL_PROCESS: process (SEL,A,B)
> begin
> case SEL is
> when "0" => SIG <= A;
> when others => SIG <= B;
> end case;
> end process SEL_PROCESS;
> end RTL;
> -------------------------------------------------------
>


--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~
Jim Lewis
Director of Training private.php?do=newpm&u=
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ~~~~~~~~~~~

Jim Lewis

The Vital library provides "VitalMux" function.
You can take a look at it as the vital src code is shipped with standard
simulators. For e.g. ncvhdl/ncsim simulator ships it in
<installation_dir>/tools/inca/files/IEEE.src/prmtvs_b.vhd. It should
also be faster as vital library is accelerated in simulators.

VitalMux calls VInterMux that does the real work.
Look at VInterMux function if you dont want to use vital library.

rgds
-Amit.


Jim Lewis wrote:
> Pasacco,
> Perhaps you want to consider using functions to implement
> this rather than an entity.
>
> Cheers,
> Jim
>
>
>> Hi
>>
>> I want to make the following two simple 4-to-1 and 2-to-1 mux, into one
>> entity with parameterized ports.
>> I am trying generic statement, yet with no success --:
>> Could someone give some idea?
>> Thankyou
>>
>>
>> --------------------------------------------------------------
>> -- 4-to-1 Mux
>> library IEEE;
>> use IEEE.std_logic_1164.all;
>> use IEEE.std_logic_arith.all;
>>
>> entity mux_gate is
>> port ( SEL: in STD_LOGIC_VECTOR (1 downto 0);
>> A,B,C,D: in STD_LOGIC;
>> SIG: out STD_LOGIC);
>> end mux_gate;
>>
>> architecture RTL of mux_gate is
>> begin
>> SEL_PROCESS: process (SEL,A,B,C,D)
>> begin
>> case SEL is
>> when "00" => SIG <= A;
>> when "01" => SIG <= B;
>> when "10" => SIG <= C;
>> when others => SIG <= D;
>> end case;
>> end process SEL_PROCESS;
>> end RTL;
>> ---------------------------------------------------
>> -- 2-to-1 Mux
>> library IEEE;
>> use IEEE.std_logic_1164.all;
>> use IEEE.std_logic_arith.all;
>>
>> entity mux_gate is
>> port ( SEL: in STD_LOGIC;
>> A,B: in STD_LOGIC;
>> SIG: out STD_LOGIC);
>> end mux_gate;
>>
>> architecture RTL of mux_gate is
>> begin
>> SEL_PROCESS: process (SEL,A,B)
>> begin
>> case SEL is
>> when "0" => SIG <= A;
>> when others => SIG <= B;
>> end case;
>> end process SEL_PROCESS;
>> end RTL; -------------------------------------------------------
>>
>
>

Amit Dua