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VHDL - Variable 'variable lengths'

 
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Old 05-08-2005, 04:54 AM   #1
Default Variable 'variable lengths'


Hi

I'm writing some code for simulation only (not synthesis). Is there
someway of declaring a unsigned variable's length in the body of a
function? So far I haven't had any success because you need to declare
the variable and its length before the body of the function, and you
can't declare an unconstrained variable.

Thanks

Taras



Taras_96
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Old 05-08-2005, 05:54 AM   #2
Mike Treseler
 
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Default Re: Variable 'variable lengths'
Taras_96 wrote:

> Is there
> someway of declaring a unsigned variable's length in the body of a
> function?


reference the length of the actual
argument right in the variable declaration
-- ...
)
return unsigned is
variable reg_v : unsigned(vec_arg'range);
begin
-- ...

> So far I haven't had any success because you need to declare
> the variable and its length before the body of the function, and you
> can't declare an unconstrained variable.


No, but you can use an unconstrained parameter.

-- Mike Treseler


Mike Treseler
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Old 05-09-2005, 01:58 AM   #3
Taras_96
 
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Default Re: Variable 'variable lengths'
Thanks Mike



Taras_96
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