pulse streatcher

Hi,

Could someone suggest me a circuit to get the below ouput from the
input?

__________________________________
| |
____| |______________________ Input


_____
| |
____| |______________________ Output


Thanks.

Praveen

On 6 May 2005 14:26:11 -0700, "Praveen" <> wrote:

>Hi,
>
>Could someone suggest me a circuit to get the below ouput from the
>input?
>
> __________________________________
> | |
>____| |______________________ Input
>
>
> _____
> | |
>____| |______________________ Output
>
>
>Thanks.

module pulse(..., in, out);
....
input in;
output out;

wire indlyd = DELAY(in);
wire out = !indlyd & in;
endmodule

now of course the interesting part inside DELAY and the missing ports.
One very crude way is to instantiate some delays between in and
indlyd. Or declare indyd as register and clock in through some number
of cycles. This depends on whether you have a clock to which in is
synchronous or how wide you want the pulse to be etc.

mk

Praveen wrote:

> Could someone suggest me a circuit to get the below ouput from the
> input?
>
> __________________________________
> | |
> ____| |______________________ Input
>
>
> _____
> | |
> ____| |______________________ Output
>

_ _ _
| | | | | ...
____| |_| |_| clock


Sample Input with the rising_edge of clock. If Input is high, set output
high. With the next rising_edge of clock, if output is high, set it low
/and/ store the information, that Input was already high. Do not set
Output high, if the stored information says, that Input was already
high. Reset this information with the rising_edge of clock, if Input is low.
Hint: In the 2nd. sentence is an "error", because I did not want to
mention the stored information so early there.

Note: The rising_edge of Output will have a delay respective to Input.

Finally: This is a "pulse compressor", not a "pulse stretcher"

Ralf

Ralf Hildebrandt