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VHDL - cf_fft

 
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Old 05-04-2005, 08:39 AM   #1
Default cf_fft


Hi guys,

a wrote a gouple of days ago a question about the cf_fft from
opencores.org.
Anyway i want to thank Bert because he helped me( my mistake wasthat i
made a error by changig the design from numeric package to arith
package.
Now the system is running, but as i said before its "only" a part of
the overall system and i got no time from my supervisor to design my
own fft ( i wish i had).
My problem is that i need to know the value of each single bit at the
in oroutput(sign 2^?), i tried it with sinewaves( to find real and im
parts of the frequency
bins),i tried also some dc values because i thought their would be a
zero frequency bin. Farther i tried noise and combinations of those
signals, but i was not able to find the specific characters of each
signal.
I think it's only a trivial thing that i don't see, but it's not my
design and it's designed with a generation tool (8000 lines)whitch
makes it impossible to read the code.

Greetings Marco



shgjoker@gmx.de
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Old 05-04-2005, 10:44 AM   #2
Neo
 
Posts: n/a
Default Re: cf_fft
marco,
I think its quite impossible to help you on this. The core is from
opencores and all the details will be implementation specific. So its
useless to post here, instead try posting in opencores forums.



Neo
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Old 05-04-2005, 11:09 PM   #3
info_
 
Posts: n/a
Default Re: cf_fft
wrote:
> Hi guys,
>
> a wrote a gouple of days ago a question about the cf_fft from
> opencores.org.
> Anyway i want to thank Bert because he helped me( my mistake wasthat i
> made a error by changig the design from numeric package to arith
> package.
> Now the system is running, but as i said before its "only" a part of
> the overall system and i got no time from my supervisor to design my
> own fft ( i wish i had).
> My problem is that i need to know the value of each single bit at the
> in oroutput(sign 2^?), i tried it with sinewaves( to find real and im
> parts of the frequency
> bins),i tried also some dc values because i thought their would be a
> zero frequency bin. Farther i tried noise and combinations of those
> signals, but i was not able to find the specific characters of each
> signal.
> I think it's only a trivial thing that i don't see, but it's not my
> design and it's designed with a generation tool (8000 lines)whitch
> makes it impossible to read the code.
>
> Greetings Marco


You should try to get all the documentation you can about this
generated fft. I don't have a very good impression, and my simulation
results are a bit weird too (but I see the input noise and some high
bins when I inject noise + Sinewave), so I guess the data_in has another
format than the one I tried (tried I on data_0 and Q on data_1), and
it may also not support a continuous flow. But I havent reead the
documentation, so it's ont very serious.
Since the VHDL "source" is not much more than a netlist (probably as useless),
I would see this as another incentive to abandonning it and using a
vendor's macro. These macros are now quite good, well documented, and
very efficient.
If you dont have much time and want an efficient FFT in your project,
using the vendor's macro might well be the way to go....
This or rewriting your own radix-based FFT.

Bert Cuzeau




info_
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