Case statement illusions ?

Info,
The code above given by you for onehot did sysnthesize differently. the
"case" version systhesized to 3 LUT's involving only OR gates and didnt
infer priority structure infact it optimized as you have mentioned to a
series of OR gates. But the "if" version systhesiszed to 6 LUT's and
inferred a priority structure. Leonardo was used for the systhesis.

Neo

Hi Symon,
for (most) of the given examples case and if-elsif will give the same result.
Why?
Because in both cases your selector is fully covered (uses all of the bits of a vector or whatever you use as a
selector). Your if-elsif collapses into a parallel structure, because there is no priority of one value over the other
possible.

but how about this:

Selector <= A&B&C; -- I MUST do this for a case statement !
case Selector is
when "001" => Output <= Input1;
when "010" => Output <= Input2;
when "100" => Output <= Input2;
when others => Output <= (others => 'Z');
end case;

vs.

If C = '1' then
Output <= Input1;
elsif B= '1' then
Output <= Input2;
elsif C= '1' then
Output <= Input3;
else
Output <= (others => 'Z');
end if;

NOW the case produces a parallel multiplexer structure that is sensitive for the given code of Selector.
The if-elsif does something different. Whenever C becomes '1' (No matter how unlikely or unneccesary this might be in
your particular design) it switches Input1 to the output. Here we have the always cited priority encoder.

To get the same functionality with a case you have to write a different code:

Selector <= A&B&C; -- I MUST do this for a case statement !
case Selector is
when "--1" => Output <= Input1;
when "-10" => Output <= Input2;
when "100" => Output <= Input2;
when others => Output <= (others => 'Z');
end case;

Now the first >when< hits whenever C becomes '1'.
This code might produce something more "parallel" than the if-elsif, but who knows about the tricks of modern synthesis
tools.

Have a nice synthesis

Eilert

backhus

Neo wrote:
> Info,
> The code above given by you for onehot did sysnthesize differently. the
> "case" version systhesized to 3 LUT's involving only OR gates and didnt
> infer priority structure infact it optimized as you have mentioned to a
> series of OR gates. But the "if" version systhesiszed to 6 LUT's and
> inferred a priority structure. Leonardo was used for the systhesis.
>
Yes my point exactly. Not all tools do this correctly. Leoanrdo is right.
Just try Precision Synthesis (or other tools) if you can and compare
the results.

The if .. elsif is a priority encoder which has a well defined behavior
for the overlapping cases (more than one 1 in the vector), and this
requires more logic than the "pure one hot". This edscription is
more predictible acroos tools.


Bert

info_

backhus wrote:

> Hi Symon,
> for (most) of the given examples case and if-elsif will give the same
> result.
> Why?
> Because in both cases your selector is fully covered (uses all of
> the bits of a vector or whatever you use as a selector). Your if-elsif
> collapses into a parallel structure, because there is no priority of one
> value over the other possible.
>
> but how about this:
>
> Selector <= A&B&C; -- I MUST do this for a case statement !
> case Selector is
> when "001" => Output <= Input1;
> when "010" => Output <= Input2;
> when "100" => Output <= Input2;
> when others => Output <= (others => 'Z');
> end case;
>
> vs.
>
> If C = '1' then
> Output <= Input1;
> elsif B= '1' then
> Output <= Input2;
> elsif C= '1' then
> Output <= Input3;
> else
> Output <= (others => 'Z');
> end if;
>
> NOW the case produces a parallel multiplexer structure that is sensitive
> for the given code of Selector.
> The if-elsif does something different. Whenever C becomes '1' (No matter
> how unlikely or unneccesary this might be in your particular design) it
> switches Input1 to the output. Here we have the always cited priority
> encoder.
>
> To get the same functionality with a case you have to write a different
> code:
>
> Selector <= A&B&C; -- I MUST do this for a case statement !
> case Selector is
> when "--1" => Output <= Input1;
> when "-10" => Output <= Input2;
> when "100" => Output <= Input2;
> when others => Output <= (others => 'Z');
> end case;
>
> Now the first >when< hits whenever C becomes '1'.
> This code might produce something more "parallel" than the if-elsif, but
> who knows about the tricks of modern synthesis tools.
>
> Have a nice synthesis
>
> Eilert

Just a few errors :

1. you can in fact qualify the expression and not use a signal.
A variable is usually preferable if you want one (otherwise,
you must add Selector in your sensitivity list, and this slows down
the simulation without usefulness).

case SLV3'(A&B&C) is -- with subtype SLV3 is std_logic_vector (3 downto 0);

2.
output <= 'Z' infers a tristate, nothing to do with a don't care!
A don't care '-' does eliminate C from the result.

3. case ... is when "--1" is wrong !
Comparing anything (but a '-') to '-' produces a false.
Comparing with '-' (to ignore the comparison) requires the use
of std_match (not usable in case statement).


VHDL is not always intuitive...


Bert Cuzeau

info_