Variable to signal assignment

Hello all
I was wondering if it was possible (read synthesizable) to assign a
variable to a signal in a clocked process *outside* the reset/clock
edge condition.

My basic idea is to use a variable instead of an intermediate signal.
Here is what I have in mind (basic "heartbeat" led)

process (clk, rst) is
variable cntr : natural range 0 to DIV - 1;
variable led : std_ulogic;
begin -- process
if rst = '1' then
cntr <= 0;
led := '0';
elsif rising_edge(clk) then
if clk_en = '1' then
if cntr = 0 then
cntr <= DIV - 1;
led := not led;
else
cntr := cntr - 1;
end if;
end if;
end if;
htbt_led <= led; -- <- is this OK?
end process;

Nicolas

Nicolas Matringe

Yes.

Best regards,

Charles

charles.elias@wpafb.af.mil

Nicolas Matringe wrote:

> I was wondering if it was possible (read synthesizable) to assign a
> variable to a signal in a clocked process *outside* the reset/clock
> edge condition.

Yes. This works as expected to wire a
variable value to a port or signal output.
It synthesizes a wire cleanly for
all tools I have tested it on.

Because the statement.

htbt_led <= led_v;

is executed for both edges of
clock and reset, the signal/port output
reset style *automatically* matches the
the output variable, and a duplicate
output register is avoided.

Logic other than output assignments
should be kept inside the if statement
to avoid synthesis of flops using
the falling clock edge.

Note that you can accomplish the same
thing *inside* the if statement
by manually matching a signal/port reset to
the output variable, that is

if rst = '1' then
cntr <= 0;
led := '0'; -- variable reset assignment
htbt_led <= '0' -- matching port/signal assignment
elsif rising_edge(clk) then
-- etc


-- Mike Treseler

Mike Treseler