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VHDL - Interfacing Digital Camera

 
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Old 04-29-2005, 01:29 AM   #1
Default Interfacing Digital Camera


Hai all!
I am a newbie in VHDL. And my project involves interfacing digital
camera with FPGA. May I know the ways I can do it?



Deepa
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Old 04-29-2005, 03:05 AM   #2
Tim Hubberstey
 
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Default Re: Interfacing Digital Camera
Deepa wrote:
> Hai all!
> I am a newbie in VHDL. And my project involves interfacing digital
> camera with FPGA. May I know the ways I can do it?


if method = "do_it_myself" then
specification <= research & write;
comp.lang.vhdl <= questions(reasonable);
code <= write & debug;
happy <= true;

elsif find(sucker) = true then
happy <= true;
task <= sucker;

else
if balance(bank) > $10000 then
report "Ouch!" severity note;
task <= consultant($10000);
happy <= true;

else
happy <= false;
end if;

--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com


Tim Hubberstey
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Old 04-29-2005, 11:39 AM   #3
Taras_96
 
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Default Re: Interfacing Digital Camera
*lol*



Taras_96
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Old 04-29-2005, 03:42 PM   #4
Jerry Coffin
 
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Default Re: Interfacing Digital Camera
Tim Hubberstey wrote:

[ ... your code seems to have a bug or two: ]

> elsif find(sucker) = true then


There's never a reason (IMO) to compare to true -- after all, if you're
comparing to true, you must already have a boolean, which is what the
comaparison also produces, so:

elsif find(sucker) then

> happy <= true;
> task <= sucker;


I suspect you really meant:

sucker <= task;

I.e. assigning the task to the sucker.

--
Later,
Jerry.

The universe is a figment of its own imagination.



Jerry Coffin
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Old 04-30-2005, 04:33 AM   #5
Tim Hubberstey
 
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Default Re: Interfacing Digital Camera
Jerry Coffin wrote:
> Tim Hubberstey wrote:
>
> [ ... your code seems to have a bug or two: ]
>
>
>>elsif find(sucker) = true then

>
>
> There's never a reason (IMO) to compare to true -- after all, if you're
> comparing to true, you must already have a boolean, which is what the
> comaparison also produces, so:
>
> elsif find(sucker) then


Not really a bug, just redundant. That's what happens when you code on
the fly without checking the result.

>> happy <= true;
>> task <= sucker;

>
>
> I suspect you really meant:
>
> sucker <= task;
>
> I.e. assigning the task to the sucker.


This all depends on your point of view. Assigning the sucker to the task
is, I believe, an equally valid expression.

Perhaps what is really needed here is some kind of bi-directional
assignment operator, like a transmission gate. I propose a new operator,
the "equivalence" operator, with symbol "<=>", for situations like this.

--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com


Tim Hubberstey
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Old 04-30-2005, 03:14 PM   #6
DAVID BINNIE
 
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Default Re: Interfacing Digital Camera
Thanks Tim,

Deepa should also be aware that his supervisor reads the newsgroups too !

Dr B


"Tim Hubberstey" <> wrote in message
news:vDgce.8995$HR1.1403@clgrps12...
> Deepa wrote:
> > Hai all!
> > I am a newbie in VHDL. And my project involves interfacing digital
> > camera with FPGA. May I know the ways I can do it?

>
> if method = "do_it_myself" then
> specification <= research & write;
> comp.lang.vhdl <= questions(reasonable);
> code <= write & debug;
> happy <= true;
>
> elsif find(sucker) = true then
> happy <= true;
> task <= sucker;
>
> else
> if balance(bank) > $10000 then
> report "Ouch!" severity note;
> task <= consultant($10000);
> happy <= true;
>
> else
> happy <= false;
> end if;
>
> --
> Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
> Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
> Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com





DAVID BINNIE
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Old 04-30-2005, 11:01 PM   #7
info_
 
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Default Re: Interfacing Digital Camera
Deepa wrote:
> Hai all!
> I am a newbie in VHDL. And my project involves interfacing digital
> camera with FPGA. May I know the ways I can do it?
>


Aye !

We wrote a short Apnote :
http://www.alse-fr.com/ALSE_Video.pdf
or if you prefer English :
http://www.alse-fr.com/English/ALSE_Video_us.pdf

You'll see page 5 how we connected an Omnivision camera to the
Nios Cyclone 1C20 board (in fact, to one if the SantaCruz extension,
the other being populated wit hthe lancelot Ramdac board.)
We used the PS2 interace of Lancelot for the I2C camera I/F.

It was really easy to set up this demonstrator.
(the Nios Cyclone board is an excellent platform)
-just don't forget to remove the Compact Flash card if you have one-

Bert Cuzeau


info_
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