Synplify warning CL209

Hello,

When synthezing the design with Synplify Pro 8.0 it gave the
follwoing Warning.

CL209 Input port bit <4> of spi_addrs(4 downto 0) is unsed.
CL209 Input port bit <3> of spi_addrs(4 downto 0) is unsed.
CL209 Input port bit <2> of spi_addrs(4 downto 0) is unsed.
CL209 Input port bit <1> of spi_addrs(4 downto 0) is unsed.


I am sure that I am using the slice (4 downto 1) as an input to the
mux.

I tried by assigning this slice to an intermediate wire (signal) and
then to the mux input . But again it is giving the same error.

Following is the relevant piece of code....
ntity Ctrl_Ram is
port(
Ctrl_Data_In : in WORD;
Ctrl_Addrs : in unsigned(3 downto 0);
Spi_Addrs : in unsigned(4 downto 0);
Ctrl_Wr : in std_logic;

Intl_Rst : in std_logic;
Clk : in std_logic;

Reset : in std_logic;

Data32_Out : out DWORD;
Data16_Out : out WORD
);
end entity Ctrl_Ram;

Architecture arch of Ctrl_Ram is
begin
spi_addrs_intl <= Spi_Addrs(4 downto 1);
Addrs_Muxrocess(Ctrl_Addrs,spi_addrs_intl,Intl_R st)
begin
case Intl_Rst is
when '0' => Addrs_In <= spi_addrs_intl;
when '1' => Addrs_In <= Ctrl_Addrs;

when others => Addrs_In <= (others =>'X');
end case;
end process Addrs_Mux;


Thank you.

-- Mohammed A Khader.

Mohammed A Khader

Mohammed A Khader wrote:
> Hello,
>
> When synthezing the design with Synplify Pro 8.0 it gave the
> follwoing Warning.
>
> CL209 Input port bit <4> of spi_addrs(4 downto 0) is unsed.
> CL209 Input port bit <3> of spi_addrs(4 downto 0) is unsed.
> CL209 Input port bit <2> of spi_addrs(4 downto 0) is unsed.
> CL209 Input port bit <1> of spi_addrs(4 downto 0) is unsed.
>
>
> I am sure that I am using the slice (4 downto 1) as an input to the
> mux.
>
> I tried by assigning this slice to an intermediate wire (signal) and
> then to the mux input . But again it is giving the same error.
>
> Following is the relevant piece of code....
> ntity Ctrl_Ram is
> port(
> Ctrl_Data_In : in WORD;
> Ctrl_Addrs : in unsigned(3 downto 0);
> Spi_Addrs : in unsigned(4 downto 0);
> Ctrl_Wr : in std_logic;
>
> Intl_Rst : in std_logic;
> Clk : in std_logic;
>
> Reset : in std_logic;
>
> Data32_Out : out DWORD;
> Data16_Out : out WORD
> );
> end entity Ctrl_Ram;
>
> Architecture arch of Ctrl_Ram is
> begin
> spi_addrs_intl <= Spi_Addrs(4 downto 1);
> Addrs_Muxrocess(Ctrl_Addrs,spi_addrs_intl,Intl_R st)
> begin
> case Intl_Rst is
> when '0' => Addrs_In <= spi_addrs_intl;
> when '1' => Addrs_In <= Ctrl_Addrs;
>
> when others => Addrs_In <= (others =>'X');
> end case;
> end process Addrs_Mux;
>
>
> Thank you.
>
> -- Mohammed A Khader.
>

1. Why this complex code and not simply :

Addrs_In <= Spi_Addrs(4 downto 1) when Intl_Rst='0' else Ctrl_Addrs;

2. I don't think we see enough of the code to tell you where
exactly you got it wrong.
Maybe Addrs_In is not used when Intl_Rst='0' ?

Have you checked with simulation that somehow Spi_Addrs is
effectively used ?


Bert Cuzeau

Bert Cuzeau

Mohammed A Khader wrote:
> Hello,
>
> When synthezing the design with Synplify Pro 8.0 it gave the
> follwoing Warning.
>
> CL209 Input port bit <4> of spi_addrs(4 downto 0) is unsed.
> CL209 Input port bit <3> of spi_addrs(4 downto 0) is unsed.
> CL209 Input port bit <2> of spi_addrs(4 downto 0) is unsed.
> CL209 Input port bit <1> of spi_addrs(4 downto 0) is unsed.
>
>
> I am sure that I am using the slice (4 downto 1) as an input to the
> mux.
>
> I tried by assigning this slice to an intermediate wire (signal) and
> then to the mux input . But again it is giving the same error.
>
> Following is the relevant piece of code....
> ntity Ctrl_Ram is
> port(
> Ctrl_Data_In : in WORD;
> Ctrl_Addrs : in unsigned(3 downto 0);
> Spi_Addrs : in unsigned(4 downto 0);
> Ctrl_Wr : in std_logic;
>
> Intl_Rst : in std_logic;
> Clk : in std_logic;
>
> Reset : in std_logic;
>
> Data32_Out : out DWORD;
> Data16_Out : out WORD
> );
> end entity Ctrl_Ram;
>
> Architecture arch of Ctrl_Ram is
> begin
> spi_addrs_intl <= Spi_Addrs(4 downto 1);
> Addrs_Muxrocess(Ctrl_Addrs,spi_addrs_intl,Intl_R st)
> begin
> case Intl_Rst is
> when '0' => Addrs_In <= spi_addrs_intl;
> when '1' => Addrs_In <= Ctrl_Addrs;
>
> when others => Addrs_In <= (others =>'X');
> end case;
> end process Addrs_Mux;

I don't see anything wrong with your code, other than being
unnecessarily complex.

This warning from Synplify usually comes from the optimization phase. It
typically means that the signal referred to does not enter into the
reduced equation of any output or stored internal state. This can be
either because you have a logic error somewhere in your design, or
because interaction with some other signal(s) causes the result to not
depend on the flagged signal. In other words, you have to examine the
total portion of the design that includes the entity in question.

This type of warning is an extremely common in large and/or
parameterized designs. It needs to be investigated to make sure the
optimization is reasonable, but it isn't something to panic over.
--
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.com

Tim Hubberstey

If Addrs_In is unused, then the references to spi_addrs will
be pruned leaving spi_addrs unused.

Mohammed A Khader wrote:

> Hello,
>
> When synthezing the design with Synplify Pro 8.0 it gave the
> follwoing Warning.
>
> CL209 Input port bit <4> of spi_addrs(4 downto 0) is unsed.
> CL209 Input port bit <3> of spi_addrs(4 downto 0) is unsed.
> CL209 Input port bit <2> of spi_addrs(4 downto 0) is unsed.
> CL209 Input port bit <1> of spi_addrs(4 downto 0) is unsed.
>
>
> I am sure that I am using the slice (4 downto 1) as an input to the
> mux.
>
> I tried by assigning this slice to an intermediate wire (signal) and
> then to the mux input . But again it is giving the same error.
>
> Following is the relevant piece of code....
> ntity Ctrl_Ram is
> port(
> Ctrl_Data_In : in WORD;
> Ctrl_Addrs : in unsigned(3 downto 0);
> Spi_Addrs : in unsigned(4 downto 0);
> Ctrl_Wr : in std_logic;
>
> Intl_Rst : in std_logic;
> Clk : in std_logic;
>
> Reset : in std_logic;
>
> Data32_Out : out DWORD;
> Data16_Out : out WORD
> );
> end entity Ctrl_Ram;
>
> Architecture arch of Ctrl_Ram is
> begin
> spi_addrs_intl <= Spi_Addrs(4 downto 1);
> Addrs_Muxrocess(Ctrl_Addrs,spi_addrs_intl,Intl_R st)
> begin
> case Intl_Rst is
> when '0' => Addrs_In <= spi_addrs_intl;
> when '1' => Addrs_In <= Ctrl_Addrs;
>
> when others => Addrs_In <= (others =>'X');
> end case;
> end process Addrs_Mux;
>
>
> Thank you.
>
> -- Mohammed A Khader.
>

Ken McElvain

If Addrs_In is unused, then the references to spi_addrs will
be pruned leaving spi_addrs unused.

Mohammed A Khader wrote:

> Hello,
>
> When synthezing the design with Synplify Pro 8.0 it gave the
> follwoing Warning.
>
> CL209 Input port bit <4> of spi_addrs(4 downto 0) is unsed.
> CL209 Input port bit <3> of spi_addrs(4 downto 0) is unsed.
> CL209 Input port bit <2> of spi_addrs(4 downto 0) is unsed.
> CL209 Input port bit <1> of spi_addrs(4 downto 0) is unsed.
>
>
> I am sure that I am using the slice (4 downto 1) as an input to the
> mux.
>
> I tried by assigning this slice to an intermediate wire (signal) and
> then to the mux input . But again it is giving the same error.
>
> Following is the relevant piece of code....
> ntity Ctrl_Ram is
> port(
> Ctrl_Data_In : in WORD;
> Ctrl_Addrs : in unsigned(3 downto 0);
> Spi_Addrs : in unsigned(4 downto 0);
> Ctrl_Wr : in std_logic;
>
> Intl_Rst : in std_logic;
> Clk : in std_logic;
>
> Reset : in std_logic;
>
> Data32_Out : out DWORD;
> Data16_Out : out WORD
> );
> end entity Ctrl_Ram;
>
> Architecture arch of Ctrl_Ram is
> begin
> spi_addrs_intl <= Spi_Addrs(4 downto 1);
> Addrs_Muxrocess(Ctrl_Addrs,spi_addrs_intl,Intl_R st)
> begin
> case Intl_Rst is
> when '0' => Addrs_In <= spi_addrs_intl;
> when '1' => Addrs_In <= Ctrl_Addrs;
>
> when others => Addrs_In <= (others =>'X');
> end case;
> end process Addrs_Mux;
>
>
> Thank you.
>
> -- Mohammed A Khader.
>

Ken McElvain