Sync + FIFO

Hi,

what does have more advantages when trying to synchronize an incoming external
datastream:

1. Synchronize the data bus with some (two or three) register stages
and feed the sychronized data into a FIFO which is an additional
synchronization stage (write clock of FIFO has a different frequency
than the read clock)

OR

2. Feed the data bus directly into the FIFO and synchronize the data coming
out of the FIFO into some (two or three) register stages ?

I am very thankful for any comments.

Rgds
André

ALuPin

ALuPin wrote:
> Hi,
>
> what does have more advantages when trying to synchronize an incoming external
> datastream:
>
> 1. Synchronize the data bus with some (two or three) register stages
> and feed the sychronized data into a FIFO which is an additional
> synchronization stage (write clock of FIFO has a different frequency
> than the read clock)
>

It makes no sense to say that you are going to "synchronize the data bus
with some register stages". What will invariably happen when you try to
do that is that some of the portions of the data bus will occasionally
exit the last stage on different clocks. Each individual bit of the bus
may be synchronized correctly, but the bus as a whole will not, without
taking additional measures.

> 2. Feed the data bus directly into the FIFO and synchronize the data coming
> out of the FIFO into some (two or three) register stages ?
>

Why do you need to synchronize the data coming out of the fifo? As you
pointed out, the read clock is different from the write clock. So the
work of synchronizing is already done for you. This is in fact a very
good way of synchronizing a bus.

Duane Clark

Just use an "asynchronous" FIFO design which is ideally suited for this
application. It uses a dual-ported RAM to separate the two clock
domains (write and read). And it can also handle the special cases of
EMPTY and FULL. That's where the two clock domains meet and where any
FIFO design gets tricky, We tested our Virtex-4 hard FIFO design (in
every BlockRAM) at 200 MHz write and ~500 MHz read clocking for many
hundred hours without any problems.
Peter Alfke, Xilinx

Peter Alfke

While the idea of using core made by the FPGA companies like Xilinx
Altera etc and while those core if done properly will give not only
good performance but also minimum use of resources I believe in this
case it is a fast solution which will work but a bad one.

Base on the way the question was put I believe the person want to have
asynchronous FIFO however have no knowledge how to do it.

In such case, to use something which was done by other, without the
understanding as how exactly the implementation is done and as such
what the pro and con, mean maybe solving the problem but without
getting the knowledge and understanding.

This is something like telling a new Math student who need to solve 1+1
or 5x7 not how to solve those equations but rather to buy a calculator
....

It might be a better solution if Xilinx have an App note as how to do
it and provide it and only after this Eng learn and understand the App
note and know how to make Async FIFO by himself, than he should use
Xilinx Core or Altera or anyone else for that matter.

Have fun.

Berty

Berty, I disagree.
While it is good for every young engineer to learn the basic skills,
designing an asynchronous FIFO is far from "basic".
Using a dual-ported RAM makes most of the design trivial, but the EMPTY
and FULL detection and arbitration at high asynchronous clock rates is
far from simple. I have a few patents and several magazine articles,
and Clifford Cummings has published extensively. It is still considered
wizardry, and grown men can get into deep arguments, since this
involves Gray counter decoding and metastability. It is much safer to
use a proven circuit designed by experts. It may sometimes be overkill,
but it works, and lets you spend your energy on the really important
and unique parts of your design.
Peter Alfke, Xilinx Applications

Peter Alfke

Hi Peter,

> It is much safer to use a proven circuit designed by experts. It may
> sometimes be overkill, but it works, and lets you spend your energy on the
> really important and unique parts of your design.

As commercially biased as I am, I have to agree with you.

Designing a good dual-clock FIFOs can take many weeks of devising
algorithms, testing them, throwing them out of the (for stress relief,
preferrably closed) window etc. When I designed my first cross-clock bus it
was on OTP parts, so I truly learned to simulate before burning, and even
then it took me six or seven failing designs (equalling 3 fully equipped
worth about $800 each) before getting it Right.

If you have three or four weeks of spare time and a powerful computer to
research the subject, then by all means, please do find an efficient way to
build a dual-clock FIFO construct we haven't thought of. Otherwise, please
use $VENDOR's implementation. Project pressure usually is way too high to
waste on a FIFO.

Best regards,


Ben

Ben Twijnstra

Peter Alfke wrote:
> Berty, I disagree.
> While it is good for every young engineer to learn the basic skills,
> designing an asynchronous FIFO is far from "basic".
> Using a dual-ported RAM makes most of the design trivial, but the EMPTY
> and FULL detection and arbitration at high asynchronous clock rates is
> far from simple. I have a few patents and several magazine articles,
> and Clifford Cummings has published extensively. It is still considered
> wizardry, and grown men can get into deep arguments, since this
> involves Gray counter decoding and metastability. It is much safer to
> use a proven circuit designed by experts. It may sometimes be overkill,
> but it works, and lets you spend your energy on the really important
> and unique parts of your design.
> Peter Alfke, Xilinx Applications
>

Excellent post IMO.
We (who spend weeks coding complex designs) are _so_ happy that gifted
engineers took the pain to build asynchronous stuffs that _work_,
guaranteed
Clock domain crossing isn't usually a problem thanks to these
little "cores" that we use everyday without thinking.

Interestingly, it seems that, today, fewer and fewer engineers are
even curious to know how modern FFT cores are implemented internally !

Well, I believe there is still room for creativity and clever engineering,
but the level of abstraction is just moving up one other notch.
The challenge also moved towards verification, but I think there is no
verification methodology which will ever fix a poor design.

But thanks again anyway to the creators of the async Fifos !!!

Bert Cuzeau

info_

Duane Clark wrote:
>It makes no sense to say that you are going to "synchronize the data bus
>with some register stages". What will invariably happen when you try to
>do that is that some of the portions of the data bus will occasionally
>exit the last stage on different clocks. Each individual bit of the bus
>may be synchronized correctly, but the bus as a whole will not, without
>taking additional measures.

Thank you for your answers.
The external data stream I am talking about comes form an USB transceiver
which sends the data synchronous to 60MHz clk which I can use in my FPGA
as FIFO write clock. Under this assumption of synchronous data stream
the portions of the data bus will NOT occasionally exit the last stage
on different clocks, will they ?

My idea was to use additional register stages to improve the performance
of the data flow.

Rgds
André

ALuPin

ALuPin wrote:
> Duane Clark wrote:
>
>>It makes no sense to say that you are going to "synchronize the data bus
>>with some register stages". What will invariably happen when you try to
>>do that is that some of the portions of the data bus will occasionally
>>exit the last stage on different clocks. Each individual bit of the bus
>>may be synchronized correctly, but the bus as a whole will not, without
>>taking additional measures.
>
>
> Thank you for your answers.
> The external data stream I am talking about comes form an USB transceiver
> which sends the data synchronous to 60MHz clk which I can use in my FPGA
> as FIFO write clock. Under this assumption of synchronous data stream
> the portions of the data bus will NOT occasionally exit the last stage
> on different clocks, will they ?

That should work fine (assuming of course the FIFOs are designed right).
In this case, the FIFOs are doing the synchronizing, not the registers.

Duane Clark

Peter,
While I understand your point I'm afraid this is why you see so many
Eng that know just about nothing except copy paste of IP module.
Of course Async FIFO is not as simple as shift register. And of course
it involve some thinking and I would strongly recommend anyone who want
to design such thing or for that matter any new design to have DR of
more experience Eng to see how he did what he did and see how to
improve or fix the wrong.
I'm fully aware of the Empty Full having designed several FIFO of all
type and flavor.
Except for the obvious of the advantage of knowing what you do and
example as for why you should know to design by yourself can be that
Some FIFO depend on the implementation when they have one last entry
will toggle the empty while other will not.
Sometime this toggle can be more useful however if you know Zilch about
how the FIFO was design you can do nothing and have to adapt yourself
to what ever the core give even if this is not the best for the design
you do.
And talking about synconizers and Gray counter etc while to use them
correctly is important this is not rocket science, Sure to give
complete and full explanation of what Metastable is and the effect of
it in clear way and not just using "wave hand" explanation can be
challenging but the actual implementation once you understand the
meaning of it is not so difficult that one have to pass it aside and
use other proven code.
I guess it all boil down to are you an Eng who want to be a copy/paste
one or are you an Eng who want to know how to do thing and yes ONCE you
know use other if they make sense, but even for this to tell if it make
sense you need to understand and not just be another copy/paste-Eng as
more and more I for one encounter.

And all those who might give example on how they saved money, time etc
by using other FIFO and not learning how to do it the right way are
just an example as why you SHOULD learn and not just be copy paste one
and use this as example to why to use other code.

Back to Math using your own logic is equivalent to say to Eng you
should learn how to do 1+1 however to do integral of X^2 from 0 to 2 is
to complex so use calculator, I do hope university will not go with
this logic and those that do well maybe from there we get all the
copy-paste Eng's.

Remember that any minute you "Waste" today for learn how to do it
will pay thousands time in your future, when you have design which are
not simple and there is no IP and you need to draw from your own
experience, which if it involve only/mainly copy-paste without the
knowledge mean you will never become ASIC leader or Architect of new
complex designs and you will stay basic simple Designer, as no
knowledge mean poor capability.

Berty