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VHDL - Construct synthesis problem

 
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Old 04-22-2005, 05:31 AM   #1
Default Construct synthesis problem


Hi,

I read a piece of code as follows:

.....
port(a,b: IN integer; c: OUT integer);
.....

Architecture error_arch2 of math_test IS
Begin
c <= a/5;
.....

The error message for c<=a/5 in the synthesis is: The second operand
must be a power of two.

Can anybody explain it to me?


Kuan


Kuan Zhou
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Old 04-22-2005, 09:37 AM   #2
Lars Wehmeyer
 
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Default Re: Construct synthesis problem
Kuan Zhou wrote:
> The error message for c<=a/5 in the synthesis is: The second operand
> must be a power of two.


Just a guess: your synthesis library does not support division units.
Therefore, the / operator can only be used to mean right shift,
which implies a power of two as second operand.

HTH

Lars



Lars Wehmeyer
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Old 04-22-2005, 09:51 AM   #3
Mohammed A khader
 
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Default Re: Construct synthesis problem
HI Kuan,

One Arithmetic right shift is equal to ' divide by 2 '. Lets take an
example Suppose you have a 5 bit of std_logic_vector as
vec = "00110". hence it represents 6 . If you right shift the vec
once then it becomes "00011" . which represents 3. That mean Shifting
right by one time is equal to dividing by 2. Similarly Shifting Left by
1 time is equal to multiply by 2 .

Suppose if you write c <= a/4 , then what it does is just right
shift by 2 times.

I assume you know the difference between airthmetic shift and logical
shift. If not you refer to some good arithmetic book to find the
difference.



Mohammed A khader
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