synthesis using the synopsys-Design Vision

Kakkar Vipan \(AI AP D PD VI 4\)

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Posts: n/a

04-21-2005

Helllo,

I am trying to synthesize a VHDL design using the Design-Vision. The
detailed problem description is the following:

I have used the attribute "synopsys infer_mux" so that the tool infers a mux
for a CASE statement. But, after executing a
synthesis-run, the tool doesn't infers a MUX. We are using the following
commands:

set hdlin_infer_mux all
set compile_create_mux_op_hierarchy true

I would appreciate any help in this.

Regards

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