Rising, falling edge

Hi everybody,

in the Lattice EC/ECP-handbook there is shown on page 61
tCK2Q_PFU (Clock to Q delay, D-type register configuration)=0.43ns

Is that the Clock-To-Output time of an internal FPGA register (not IOs)?


Do arise any problems with tCO of the first stage when trying the following:

process(Clk)
begin
if rising_edge(Clk) then
l_sample1 <= Data;
end if;
end process;

process(Clk)
begin
if falling_edge(Clk) then
l_sample2 <= l_sample1;
end if;
end if;

Is there a problem with tCO of l_sample1 that is "l_sample2" samples "l_sample1"
although "l_sample1" has not changed yet ? (TClk=7,5ns)


Rgds
André

ALuPin