Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Simulation in modelsim.... Multiple Drivers.......

Thread Tools

Simulation in modelsim.... Multiple Drivers.......

Posts: n/a
Hi all...
i have been trying to simulate some code in which there is a data bus

that is declared to be of INOUT type. I have simulated my VHDL code and

for both read and write operations it works fine, also the data bus
gets tri-stated (Z) when not in use.
Now this simulation was done by directly putting the values of signals

in the ModelSim environment. Then I thought to write a testbench to
simulate the same. In this case when I write some data on the databus
it does not get tri-stated when not in use. So i tried to debug the
problem and found that since in my testbench I am forcing some value on

the bus say '3B' and also in code i force 'Z' when not in use, then
STD_LOGIC being a resolved type resolves the value and gives '3B' since

'Z' has got least priority.
Why it worked directly on ModelSim environment was bcoz i was
"Depositing" the value on bus and not "Freezing" it. If i freeze the
value there then in that case also i cud not make the bus tri-stated.

So i would like to know how in our testbench we can write code such
that i can see all the correct results. I think in practice this will
work fine but it's better if in simulation also we can see the desired
results. Hope somebody can help. Thanx a lot

Reply With Quote

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off

Similar Threads
Thread Thread Starter Forum Replies Last Post
Problem with post-route simulation / timing simulation jasperng VHDL 0 11-27-2008 06:23 AM
simulation of multiple shells Erich Lin Ruby 1 07-04-2006 02:34 PM
GHDL for VHDL simulation? John Williams VHDL 0 08-08-2003 12:31 AM
VHDL Simulation for Linux Neil Zanella VHDL 2 08-04-2003 01:11 PM
VHDL Simulation in ModelSim Manfred Balik VHDL 0 07-15-2003 02:12 PM