Converting synthesized VHDL/Verilog to spice netlist

Dear All,
I'm trying to get Spice netlist file from Verilog/VHDL. After I
synthesized the vhdl file using Synplify, what tools available that
can help me to get the spice netlist. I need the interconnect
information incorporated in the spice netlist. Any help will be very
useful
Thanks,
ali

Noohul Ali

I think a backend layout tool would be able to do it. at least verilog
to spice conversion is done by mentor tool.

Neo

I think a backend layout tool would be able to do it. at least verilog
to spice is done by mentors tool.

Neo