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A question about syntax of VHDL

 
 
Jim Huang
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      04-21-2005
Can I write the if condition like this? Assume

signal A std_logic_vector(29 downto 0);

if A = (others => '0) then
.................
end if;

if this syntax is invalid, how should I write it? any simple way.
I do not want to put 30 zeros here.

Can I write the condition as
A = "00" & 0x0000000

Thanks
Jim

 
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dutchgoldtony
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      04-21-2005
An assignment takes the form if A<= (others => '0');

 
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Jim Huang
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      04-21-2005
Hi

Thanks, but I think you misunderstood me. I asked if I can compare the
signal A with (other => '0') in the IF clause.

 
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charles.elias@wpafb.af.mil
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      04-21-2005
This form will work:

if Sig = (Sig'range => '0') then

This is from comp.lang.vhdl "Frequently Asked Questions" Part 1. This
very useful document can be found at http://vhdl.org/comp.lang.vhdl/.

Best regards,

Charles

 
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Mohammed A khader
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      04-21-2005
HI Jim,

> if A = (others => '0) then


will give you error as

others must be use with constrained array. (others => '0') is not
enough to know the length of the array.
>Can I write the condition as
> A = "00" & 0x0000000


Yes you can write the numbers in hex or oct

if ( A = X"0000") then -- will work fine but make sure that type A
is a vector of bit or std_logic.

-- Mohammed A Khader.

 
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Mohammed A khader
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      04-21-2005
HI Jim,

> if A = (others => '0) then


will give you error as

others must be use with constrained array. (others => '0') is not
enough to know the length of the array.
>Can I write the condition as
> A = "00" & 0x0000000


Yes you can write the numbers in hex or oct

if ( A = X"0000") then -- will work fine but make sure that type A
is a vector of bit or std_logic.

-- Mohammed A Khader.

 
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info_
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      04-24-2005
Jim Huang wrote:
> Can I write the if condition like this? Assume
>
> signal A std_logic_vector(29 downto 0);
>
> if A = (others => '0) then
> .................
> end if;
>
> if this syntax is invalid, how should I write it?


One clean solution is to use subtypes and qualified expression :

subtype SLV30 is std_logic_vector(29 downto 0);

signal A : SLV30;

if A = SLV30'(others=>'0') then -- will work

As you noticed , hexadecimal notation isn't for fun except
on exact multiple of four bits...

Other solution :

if (unsigned(A)=0 then

etc...

Bert Cuzeau


 
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