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VHDL - prfered style of coding?

 
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Old 04-21-2005, 09:42 AM   #1
Default prfered style of coding?


Hi,
I just wanted to ask which is prefered style of coding...behavioral or
structural? Which among the two fit into FPGA easily?
Thanks.



bxbxb3
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Old 04-21-2005, 01:45 PM   #2
Christian Gelinek
 
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Default Re: prfered style of coding?
Behavioral is mainly for testbenches and simulation, structural is the style
for implementation on FPGAs/CPLDs/ASICs.




Christian Gelinek
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Old 04-21-2005, 04:16 PM   #3
Ralf Hildebrandt
 
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Default Re: prfered style of coding?
bxbxb3 wrote:


> I just wanted to ask which is prefered style of coding...behavioral or
> structural?


If you have got a core of a subcomponent - use it. Somebody has done the
work for you and you don't need to do it again unless you try to do it
better or you try to expand it. -> structural

If you have a huge project - split it into smaller parts. This is more
readable for humans and the parts can be synthesized and tested
separately. -> structural

Don't break down hierarchy to the gates. (Don't try to model an adder
through instantiation of fulladder cells - use the power of your
synthesis tool which can do this better.) Find a balance between
splitting your design in parts and modelling something in one component.
-> behavioral

Try to write target-indipendent code as long as possible. (Do not use
primitive cells (except you /really/ need it). If you use IP cores,
encapsulate them into a common entity making it exchangeable by a
different IP core with the same functionality.) -> behavioral


> Which among the two fit into FPGA easily?


Not the target is important but the synthesis tool! (Write
target-indipendent code.) If your code can be synthesized (and it
performs well), everything is o.k..

There are several other facts, that become important after choosing your
target:
* latches allowed?
* (a)synchronous resets? everytime?
* both clock edges?
* divided clocks?
....
But this is indipendent from behavioral / structural design.


Ralf


Ralf Hildebrandt
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