Velocity Reviews - Computer Hardware Reviews

Velocity Reviews > Newsgroups > Programming > VHDL > Unconstrained ports for synthesis

Reply
Thread Tools

Unconstrained ports for synthesis

 
 
Mohammed A khader
Guest
Posts: n/a
 
      04-20-2005
Hi all,

I am having a component Multiplier with unconstrained ports. But this
is not my top_level_entity and ports are implicity constrained while
instanciating this component.

It simulates well but while synthezing Quartus says that ports must be
constrained. I think that Quartus could infer it from instanciation
syntax. Is there any solution to get around it

Thanks.

-- Mohammed A Khader.

 
Reply With Quote
 
 
 
 
Subroto Datta
Guest
Posts: n/a
 
      04-20-2005
Hello,

Can you be more specific as to the exact message that Quartus gives? You
can cut ans paste the Quartus message in the reply. Also can you describe
what is meant by "implictly constrainedwhile instanciating" in the post?

Subroto Datta
Altera Corp.

"Mohammed A khader" <(E-Mail Removed)> wrote in message
news:(E-Mail Removed) oups.com...
> Hi all,
>
> I am having a component Multiplier with unconstrained ports. But this
> is not my top_level_entity and ports are implicity constrained while
> instanciating this component.
>
> It simulates well but while synthezing Quartus says that ports must be
> constrained. I think that Quartus could infer it from instanciation
> syntax. Is there any solution to get around it
>
> Thanks.
>
> -- Mohammed A Khader.
>



 
Reply With Quote
 
 
 
 
Mohammed A Khader
Guest
Posts: n/a
 
      04-20-2005
Hi,

-- Error messages are......

Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(26):
ports must be constrained
Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(27): ports
must be constrained
Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(2: ports
must be constrained
Error: Can't elaborate user hierarchy
"Core:Core_Map|Datapathatapath_Map"
Error: Quartus II Analysis & Synthesis was unsuccessful. 4 errors, 0
warnings
Error: Processing ended: Wed Apr 20 16:33:52 2005
Error: Elapsed time: 00:00:05

-- My Multiplier component is .........
entity Multiplier_Synth is
port(
Op1 : in signed; -- Operator 1
Op2 : in signed; -- Operator 2
Mult_Out : out signed -- Multiplication Result
);
end entity Multiplier_Synth;

architecture Multiplier_Synth_Arch of Multiplier_Synth is
begin
Mult_Out <= Op1 * Op2;
end architecture Multiplier_Synth_Arch;

-- And it has been instantiated in an entity called Datapath_Map as
.......

signal Mux1_Out : WORD20; -- Output of Mux1
signal Mux2_Out : WORD; -- Output of Mux2
signal Mult_Out : signed(39 downto 0); -- Multiplier Output

Multiplier_Map : entity work.Multiplier_Synth(Multiplier_Synth_Arch)
port map(
Op1 => Mux1_Out,
Op2 => Mux2_Out,
Mult_Out => Mult_Out
);

Mux1_Out , Mux2_Out and Mult_Out are constrained signals . Hence
Op1,Op2,Mult_Out implicitly can be constrained by bit length of
20,20,40 respectively.

Thanks..

-- Mohammed A Khader.

 
Reply With Quote
 
Ralf Hildebrandt
Guest
Posts: n/a
 
      04-20-2005
Mohammed A Khader wrote:

> Error: VHDL Entity Declaration error at Multiplier_Synth.Vhd(26):
> ports must be constrained


> -- My Multiplier component is .........
> entity Multiplier_Synth is
> port(
> Op1 : in signed; -- Operator 1
> Op2 : in signed; -- Operator 2
> Mult_Out : out signed -- Multiplication Result
> );
> end entity Multiplier_Synth;


Use generic parameters - e.g.:


entity Multiplier_Synth is
generic(
width : integer:=16 );
port(
Op1 : in signed(width-1 downto 0);
Op2 : in signed(width-1 downto 0);
Mult_Out : out signed(width*2-1 downto 0)
);
end entity Multiplier_Synth;


Generic parameters are overridden, if a generic mapping is used during
instantiation. (Otherwise the given default value is used.)
Because you have to define the bitwidth somewhere in your design, it
does not matter where and how. Therefore Generic paramters are suitable.
You can feed them from the very bottom to the top entity.

Ralf
 
Reply With Quote
 
Subroto Datta
Guest
Posts: n/a
 
      04-20-2005
Hello Mohammed,

We will be adding support for unconstrained entity ports in 5.1,
due out later this year (we need to get 5.0 out first ). In the
interim please use the generic approach suggested by Ralf.

Hope this helps,
Subroto Datta
Altera Corp.

 
Reply With Quote
 
Ray Andraka
Guest
Posts: n/a
 
      04-21-2005
Mohammed A khader wrote:

> Hi all,
>
> I am having a component Multiplier with unconstrained ports. But this
>is not my top_level_entity and ports are implicity constrained while
>instanciating this component.
>
> It simulates well but while synthezing Quartus says that ports must be
>constrained. I think that Quartus could infer it from instanciation
>syntax. Is there any solution to get around it
>
>Thanks.
>
>-- Mohammed A Khader.
>
>
>

I do not believe the Quartus compiler supports unconstrained ports.
Either use generics to size the port, or use a synthesizer such as
synplify that does support unconstrained ports.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email http://www.velocityreviews.com/forums/(E-Mail Removed)
http://www.andraka.com

"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759


 
Reply With Quote
 
 
 
Reply

Thread Tools

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
Unconstrained integers and synthesis Thomas Heller VHDL 9 02-03-2011 07:04 PM
Unconstrained array ports - Good or Bad? Anon Anon VHDL 2 01-28-2007 07:39 PM
Unconstrained array of unconstrained vector. Amal VHDL 5 03-08-2006 05:02 PM
SOS! newbie question about synthesizable VHDL : synthesis run successfully but post-synthesis failed... walala VHDL 4 09-09-2003 08:41 AM
what are the possible reasons that successful pre-synthesis simulation + successful synthesis = failed post-synthes walala VHDL 4 09-08-2003 01:51 PM



Advertisments