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combining two EDF netlist in ISE

 
 
williams
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      04-18-2005
Hello guys,

I am working on a project which contain some IP core which is avaiable
to me in EDF netlist form. I am having the following doubt
I synthesis my verilog code in synplify and implementing this EDF in
the ISE. Now since i have my design in EDF format , how can i
instantiate a new IP core which in EDF format in my design which is
also in EDF file.

Is there a way by which i can instantiate the netlist of IP core in by
verilog code. If so how do i do that?
waiting for your reply,
Thanks and regards
williams
 
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jeremy.webb@ieee.org
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      04-18-2005
Here's some sample Verilog code:

module some_module_name (// *** Inputs ***
input [9:0] ADDR,
input CLK,
input EN,

// *** Outputs ***
output [17:0] DOUT
)/* synthesis syn_black_box */;

endmodule

Hope this helps,

Jeremy

williams wrote:
> Hello guys,
>
> I am working on a project which contain some IP core which is

avaiable
> to me in EDF netlist form. I am having the following doubt
> I synthesis my verilog code in synplify and implementing this EDF in
> the ISE. Now since i have my design in EDF format , how can i
> instantiate a new IP core which in EDF format in my design which is
> also in EDF file.
>
> Is there a way by which i can instantiate the netlist of IP core in

by
> verilog code. If so how do i do that?
> waiting for your reply,
> Thanks and regards
> williams


 
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