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I have a vhdl value that I must test whether it increments by one. The
input signal is a 32-bits count value (std logic vector). My module
would receive this value as an input to check whether it increments and
that would affect the state machine.

How would I code something like this as efficiently as possible?


Salman

Salman wrote:
> I have a vhdl value that I must test whether it increments by one. The
> input signal is a 32-bits count value (std logic vector). My module
> would receive this value as an input to check whether it increments and
> that would affect the state machine.
>
> How would I code something like this as efficiently as possible?
>
>
> Salman
>

Unclear spec.
If it' a counter with Enable (that can only be incremented by one
or remain stable. Load ??), then a simple xor gate on LSB does it !

Otherwise, an incrementor and equality comparator ?

Salman wrote:

> I have a vhdl value that I must test whether it increments by one. The
> input signal is a 32-bits count value (std logic vector). My module
> would receive this value as an input to check whether it increments and
> that would affect the state machine.
>
> How would I code something like this as efficiently as possible?
>
>
> Salman
>
Should it check if the previous value is (current-1)?
Is it unsigned or signed?
Need more spec...

EG