Synthesis problem

Hi,

When I tried to synthesize a program, I wrote:

signal a: std_logic_vector(3 downto 0):= "0110";

But when I synthesize it, the synthesis tool gives me warnings that
these initial value assigned to a are ignored in systhesis. So Finally
when I map the circuits to FPGA, I may get random value for a when
the FPGA is powered up.

Somebody suggested me to use Reset or use some codes to control the
reset when the FPGA is powered up. But I guess there may be an easier way
to solve this problem.

Kuan

Kuan Zhou

Kuan Zhou <> writes:

> Hi,
>
> When I tried to synthesize a program, I wrote:
>
> signal a: std_logic_vector(3 downto 0):= "0110";
>
> But when I synthesize it, the synthesis tool gives me warnings
> that these initial value assigned to a are ignored in systhesis.

Correct. Initial values are for simulation only.

> So
> Finally when I map the circuits to FPGA, I may get random value for a
> when
> the FPGA is powered up.
>
> Somebody suggested me to use Reset or use some codes to control
> the reset when the FPGA is powered up. But I guess there may be an
> easier way to solve this problem.

No. Use a Reset as you have been suggested.


Kai
--
Kai Harrekilde-Petersen <khp(at)harrekilde(dot)dk>

Kai Harrekilde-Petersen